poleguy looking for lost toolsMaking it match the sim.
Clock shows one clock between last data transition and rising edge of we_n, scope shows two.
Getting closer!
HabrСоздание USB контроллера на FPGA чипе и подключение клавиатуры
Здравствуйте меня зовут Дмитрий сегодня мы напишем контроллер USB шины и подключим к нему клавиатуру.
cnx-software.comAERIS-10 open-source hardware radar can track multiple objects up to 20km away
AERIS-10 open-source hardware radar can track multiple objects up to 20km away
AERIS-10 is an open-source hardware, "low-cost" (more on that later) 10.5 GHz phased array radar system featuring Pulse Linear Frequency Modulated (LFM) modulation and based on an AMD Artix-7 FPGA. Two versions are available: the AERIS-10N (Nexus), providing up to 3km range with an 8x16 patch antenna array, and the AERIS-10X (Extended), offering up to 20km range thanks to a 32x16 dielectric-filled slotted waveguide array. ARIES-10 key components and features: Main board FPGA - AMD Artix-7 XC7A100T for: PLFM Chirps generation via the DAC Raw ADC data read Automatic Gain Control (AGC) I/Q Baseband Down-Conversion Decimation Filtering Forward FFT Pulse Compression Doppler, MTI, and CFAR processing USB Interface MCU - ST STM32F746xx microcontroller for Power management FPGA communication Setup and interface with the components on the main, frequency synthesizer, and power amplifier boards, plus: GPS module for GUI map centering GY-85 IMU for pitch/roll correction of target coordinates BMP180 Barometer
PipelineC@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓
github.com/JulianKemmer...
#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec
PipelineC@nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard
#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec
PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.
github.com/JulianKemmer...
#fpga #asic #rtl #hdl #verilog #vhdl #hls #eda
PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions
Зачем нужен Design for Testability (DFT) и как его реализуют в FPGA
Привет, Хабр! Меня зовут Антон Осетров, я разрабатываю СнК в компании
https://habr.com/ru/companies/yadro/articles/1006004/
#dft #design_for_manufacturing #rtl #fpga #fpga+soc #verilog #testing #испытания #design_for_testability #atpg
Dabao board features open-source hardware Baochip-1x RISC-V MCU (Crowdfunding)
Dabao board features open-source hardware Baochip-1x RISC-V MCU (Crowdfunding)
An open-source hardware board usually features a closed-source microcontroller or processors, but the Dabao evaluation board goes further with the open-source Boachip-1x MCU, whose RTL files are available. It's also manufactured in such a way that it is inspectable with the Infra-Red, In Situ (IRIS) technique, so users can look at the silicon and confirm they’ve got the right chip in a non-destructive way. Baochip-1x is a "general-purpose" microcontroller with a 350 MHz Vexriscv RV32-IMAC CPU core, a BIO accelerator for I/Os with four 700MHz PicoRV RV32-EMC CPU cores, 4MB of ReRAM, 2MB SRAM, a USB interface, various other I/Os, and hardware secure elements such as cryptography accelerators, key stores, one-way counters, true random number generation, and hardware attack countermeasures such as glitch sensors and a security mesh. The Dabao board itself is pretty basic with the microcontroller, two 16-pin headers for I/Os, a USB-C port for power and programming,