Show threadGareth Halfacree9h ago

Then something for the #Verilog and #Factorio crowd to bond over: a tool for taking a Verilog chip design and putting into the game... as a functional factory.

Demos of its capabilities go all the way up to a 32-bit #RISCV CPU...

https://www.hackster.io/news/ben-c-s-clever-compiler-imports-verilog-designs-including-a-working-risc-v-cpu-into-factorio-87ba54aa2c51

#Technology #News #Hackster

Ben C.'s Clever Compiler Imports Verilog Designs, Including a Working RISC-V CPU, Into Factorio

Factory automation sim gets the ability to run arbitrary code on an internal CPU, thanks to a Verilog-to-Factorio toolchain.

Hackster.io
Markus Osterhoff2d ago

#TIL wie eins #Verilog-Module mit #Python testen kann: cocotb.

Damit kann ich dann die numerischen Algorithmen, bevor sie in Hardware gehen, einmal in Software und gegen numpy et al. testen; inkls. schneller Plots bzw. Bilder.

poleguy looking for lost tools2d ago

Making it match the sim.

Clock shows one clock between last data transition and rising edge of we_n, scope shows two.

Getting closer!

#protonpack #FPGA #Alchitry #Verilator #verilog

Habr6d ago

Создание USB контроллера на FPGA чипе и подключение клавиатуры

Здравствуйте меня зовут Дмитрий сегодня мы напишем контроллер USB шины и подключим к нему клавиатуру.

https://habr.com/ru/articles/1012850/

#USB #FPGA #verilog

Создание USB контроллера на FPGA чипе и подключение клавиатуры

Здравствуйте меня зовут Дмитрий сегодня мы напишем контроллер USB шины и подключим к нему клавиатуру. Железо Для начала нужно определится. Мы создадим контроллер USB версии 1.1. В отличии от USB 2.0...

Хабр
cnx-software.comMar 15

AERIS-10 open-source hardware radar can track multiple objects up to 20km away

https://fed.brid.gy/r/https://www.cnx-software.com/2026/03/15/aeris-10-open-source-hardware-radar-can-track-multiple-objects-up-to-20km-away/

AERIS-10 open-source hardware radar can track multiple objects up to 20km away

AERIS-10 is an open-source hardware, "low-cost" (more on that later) 10.5 GHz phased array radar system featuring Pulse Linear Frequency Modulated (LFM) modulation and based on an AMD Artix-7 FPGA. Two versions are available: the AERIS-10N (Nexus), providing up to 3km range with an 8x16 patch antenna array, and the AERIS-10X (Extended), offering up to 20km range thanks to a 32x16 dielectric-filled slotted waveguide array. ARIES-10 key components and features: Main board FPGA - AMD Artix-7 XC7A100T for: PLFM Chirps generation via the DAC Raw ADC data read Automatic Gain Control (AGC) I/Q Baseband Down-Conversion Decimation Filtering Forward FFT Pulse Compression Doppler, MTI, and CFAR processing USB Interface MCU - ST STM32F746xx microcontroller for Power management FPGA communication Setup and interface with the components on the main, frequency synthesizer, and power amplifier boards, plus: GPS module for GUI map centering GY-85 IMU for pitch/roll correction of target coordinates BMP180 Barometer

CNX Software - Embedded Systems News
PipelineCMar 13
@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec
PipelineCMar 13

@nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

poleguy looking for lost toolsMar 13

New blog post.

https://poleguy.com/blog/john-henry-and-the-steam-hammer.html

#AI #NoAI #AIcritic #slop #FPGA #verilog #vhdl

PipelineCMar 10
PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions. github.com/JulianKemmer... #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda
PipelineCMar 10

PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions.

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

#fpga #asic #rtl #hdl #verilog #vhdl #hls #eda