GripNews2h ago
🌘 VHDL 的核心瑰寶：論其如何維護確定性
➤ 從 Delta Cycle 看 VHDL 與 Verilog 的本質區別
✤ https://www.sigasi.com/opinion/jan/vhdls-crown-jewel/
本文深入剖析了硬體描述語言（HDL）中一個關鍵的設計哲學差異。作者將 VHDL 的「Delta Cycle」（增量週期）演算法譽為該語言的皇冠明珠，並解釋了為何該機制能確保模擬結果的確定性。相較之下，Verilog 因缺乏類似的嚴格分階段處理機制，導致在處理併發事件時容易出現非確定性的結果。作者認為，VHDL 通過將信號更新與流程評估強制分離，以極低的成本解決了併發設計中的核心問題。
+ 這篇文章精準地擊中了 Verilog 使用者的痛點。非阻塞賦值的確經常被誤用，而 VHDL 的這種嚴謹性確實讓大型複雜系統的模擬更具可靠性。
+ 很喜歡這種深入底層邏輯的分析。雖然現在 EDA 工具越來越強大，但理解 Delta Cycle 對於除錯模擬中的奇異現象（race conditions）仍然至
#HDL 設計 #VHDL #Verilog #數位電路模擬
VHDL's crown jewel

How VHDL preserves determinism In this post, I would like to talk about VHDL’s crown jewel: how it preserves determinism in a concurrent language. Here is a figure of how it works:

Sigasi
Flux17h ago
Adding an enable signal to 🏝️ Isle.Computer drawing engine was more of a pain than I expected, but we're now ready to share vram access with the CPU. On the plus side, this also allows you to slow the action down so you can see the drawing happen. #FPGA #verilog
Hacker News1d ago

A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU)

https://github.com/ben-j-c/verilog2factorio

#HackerNews #Verilog #Factorio #Compiler #RISC-V #CPU #Simulation #OpenSource

GitHub - ben-j-c/verilog2factorio

Contribute to ben-j-c/verilog2factorio development by creating an account on GitHub.

GitHub
PipelineC2d ago

Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

#hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

PipelineC2d ago
Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how? github.com/JulianKemmer... #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec
Gray Beard2d ago

SystemLisp - an HDL simulator written in Common Lisp

https://github.com/systemlisp

#lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga

systemlisp - Overview

An experimental HDL simulator written in Common Lisp focused on interactive and extensible hardware design and verification. - systemlisp

GitHub
Show threadGareth Halfacree3d ago

Then something for the #Verilog and #Factorio crowd to bond over: a tool for taking a Verilog chip design and putting into the game... as a functional factory.

Demos of its capabilities go all the way up to a 32-bit #RISCV CPU...

https://www.hackster.io/news/ben-c-s-clever-compiler-imports-verilog-designs-including-a-working-risc-v-cpu-into-factorio-87ba54aa2c51

#Technology #News #Hackster

Ben C.'s Clever Compiler Imports Verilog Designs, Including a Working RISC-V CPU, Into Factorio

Factory automation sim gets the ability to run arbitrary code on an internal CPU, thanks to a Verilog-to-Factorio toolchain.

Hackster.io
Markus Osterhoff5d ago

#TIL wie eins #Verilog-Module mit #Python testen kann: cocotb.

Damit kann ich dann die numerischen Algorithmen, bevor sie in Hardware gehen, einmal in Software und gegen numpy et al. testen; inkls. schneller Plots bzw. Bilder.

poleguy looking for lost tools6d ago

Making it match the sim.

Clock shows one clock between last data transition and rising edge of we_n, scope shows two.

Getting closer!

#protonpack #FPGA #Alchitry #Verilator #verilog

HabrMar 20

Создание USB контроллера на FPGA чипе и подключение клавиатуры

Здравствуйте меня зовут Дмитрий сегодня мы напишем контроллер USB шины и подключим к нему клавиатуру.

https://habr.com/ru/articles/1012850/

#USB #FPGA #verilog

Создание USB контроллера на FPGA чипе и подключение клавиатуры

Здравствуйте меня зовут Дмитрий сегодня мы напишем контроллер USB шины и подключим к нему клавиатуру. Железо Для начала нужно определится. Мы создадим контроллер USB версии 1.1. В отличии от USB 2.0...

Хабр