Adrian Sampson4d ago
This blog post is an extended metaphor that serves as an excuse to complain about Verilog. https://www.cs.cornell.edu/~asampson/blog/buildingblocks.html
Back to the Building Blocks’ Building Blocks

Verilog is the foundation of all hardware design, and it is fatally flawed. We should all be worried about a glut of hardware bugs caused by Verilog’s unpredictable semantics and simplistic type system.

Show threadPete Bleackley
@adrian Your post doesn't mention #VHDL at all. As far as I remember from my brief use of it about 20 years ago, it doesn't require #Verilog as an intermediate stage. Can you comment on it?
May 26 at 6:07pmWeb
Show threadAdrian Sampson4d ago
@PeteBleackley Ah yeah, great question! VHDL is sometimes the exception to the rule that "all EDA tools support Verilog and only Verilog." Not all tools support it, though, and it is sometimes a second-class citizen. For example, IIRC Yosys supports VHDL only by translating it to Verilog first via https://github.com/ldoolitt/vhd2vl !
GitHub - ldoolitt/vhd2vl

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Show threadWilliam D. Jones4d ago
@adrian @PeteBleackley Nowadays, GHDL has a yosys plugin that I've successfully used: https://github.com/ghdl/ghdl-yosys-plugin
GitHub - ghdl/ghdl-yosys-plugin: VHDL synthesis (based on ghdl)

VHDL synthesis (based on ghdl). Contribute to ghdl/ghdl-yosys-plugin development by creating an account on GitHub.

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