Icepi Zero Bot11h ago

@[email protected]

@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

Success!

UART Output

... [TRUNCATED] ... iverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! 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Hello Fediverse on UART! Hello Fed


UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;


#FPGA #Icepi-Zero #HDL #VHDL
Icepi Zero Bot15h ago

@[email protected]

@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

Success!

UART Output

... [TRUNCATED] ... Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! 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Hello Fediverse on UART!


UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;


#FPGA #Icepi-Zero #HDL #VHDL
Icepi Zero Bot15h ago

@[email protected]

@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

Success!

UART Output

... [TRUNCATED] ... ! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! 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Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! 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Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! 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Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART


UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;


#FPGA #Icepi-Zero #HDL #VHDL
Icepi Zero Bot15h ago

@[email protected]

@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

Success!

UART Output

... [TRUNCATED] ... on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! 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Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! 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Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse on UART! Hello Fediverse


UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;


#FPGA #Icepi-Zero #HDL #VHDL
Icepi Zero Bot15h ago

@[email protected]

@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

Success!

UART Output

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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;


#FPGA #Icepi-Zero #HDL #VHDL
Icepi Zero Bot16h ago

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@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

Success!

UART Output

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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;


#FPGA #Icepi-Zero #HDL #VHDL
Icepi Zero Bot16h ago

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@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

Success!

UART Output

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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;


#FPGA #Icepi-Zero #HDL #VHDL
Icepi Zero Bot17h ago

@[email protected]

@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

Success!

UART Output

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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;


#FPGA #Icepi-Zero #HDL #VHDL
Icepi Zero Bot17h ago

@[email protected]

@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 20) := "Hello Fediverse! <3" & LF; constant example_text_row : integer := 15; constant example_text_col : integer := 15; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range example_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(example_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < example_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

Success!

UART Output

... [TRUNCATED] ... <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse! <3 Hello Fediverse!


UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1191242884.9%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp41.75 MHz25 MHz$glbnet$clkt333.22 MHz250 MHz
Code

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 20) := "Hello Fediverse! <3" & LF; constant example_text_row : integer := 15; constant example_text_col : integer := 15; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range example_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(example_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < example_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;


#FPGA #Icepi-Zero #HDL #VHDL
Icepi Zero Bot18h ago

@[email protected]

@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 19) := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range example_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(example_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < example_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

Success!

UART Output

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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1375242885.7%TRELLIS_FF230242880.9%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.66 MHz25 MHz$glbnet$clkt338.87 MHz250 MHz
Code

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string(1 to 19) := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range example_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(example_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < example_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;


#FPGA #Icepi-Zero #HDL #VHDL