@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions. github.com/JulianKemmer... #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

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Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% MULT18X18D32810.7% TRELLIS_COMB125052428851.5% TRELLIS_FF145242880.6% TRELLIS_IO101975.1% TRELLIS_RAMW1200303639.5%
TimingClockAchievedConstraint $glbnet$clkp31.01 MHz25 MHz $glbnet$clkt277.32 MHz250 MHz
Code

module my_code #( parameter int WIDTH = 640, parameter int HEIGHT = 480, parameter int CONSOLE_COLUMNS = WIDTH / 8, parameter int CONSOLE_ROWS = HEIGHT / 8 )( input logic clk, input logic rst, input int px, input int py, input logic hsync, input logic vsync, input int col, input int row, output int char, output logic [23:0] foreground_color, output logic [23:0] background_color ); // version 2.0 // Fire resolution: 80x60 â scaled to 640x480 localparam int FW = 80; localparam int FH = 60; logic [7:0] fire[FH-1:0][FW-1:0]; logic old_vsync; logic [7:0] lfsr; // length of div slows frequency of sparks logic [4:0] spark_div; logic updating; logic [6:0] ux; logic [5:0] uy; assign char = 0; assign foreground_color = 24'hFFFFFF; // Scale VGA pixel to fire coordinates wire [6:0] fx = px[9:3]; // /8 â 0..79 wire [5:0] fy = py[9:3]; // /8 â 0..59 wire [7:0] v = fire[fy][fx]; // Map intensity to flame color: red dominant, green half, blue low assign background_color = {v, v >> 1, v >> 3}; integer x,y; always_ff @(posedge clk) begin if (rst) begin old_vsync <= 0; updating <= 0; ux <= 0; uy <= 0; spark_div <= 0; lfsr <= 8'hA5; // for (y=0; y<FH; y=y+1) // for (x=0; x<FW; x=x+1) // fire[y][x] <= 0; end else begin // start update on vsync rising edge (enter VBLANK) if (vsync && !old_vsync) begin updating <= 1; ux <= 0; uy <= 0; end // scroll fire upward across many clocks if (updating) begin // slight decay based on lsb of x coordinate times 2 fire[uy][ux] <= fire[uy+1][ux] - (ux & 1)<<1; if (ux == FW-1) begin ux <= 0; if (uy == FH-2) begin updating <= 0; uy <= 0; end else begin uy <= uy + 1; end end else begin ux <= ux + 1; end end // bottom sparks (slow, only when not updating) if (vsync && !old_vsync && !updating) begin spark_div <= spark_div + 1; if (!spark_div) begin lfsr <= {lfsr[6:0], lfsr[7]^lfsr[5]^lfsr[4]^lfsr[3]}; fire[FH-1][lfsr[6:0]] <= 8'hFF; end end old_vsync <= vsync; end end endmodule

#FPGA #Icepi-Zero #HDL #SystemVerilog

중성지방과 콜레스테롤, 두 마리 토끼 모두 잡는 건강관리법

중성지방과 콜레스테롤, 무엇이 다른지 알아보세요. 적절한 수치 관리 방법과 생활 습관 개선 방안을 소개합니다.

https://habitdays.com/posts/3605

Explore the state of the art in high-level hardware description languages with Jean Bruant — learn how HLS/DSLs map to VHDL & SystemVerilog, and what that means for FPGA/ASIC design. Great talk for engineers and students! #Hardware #HDL #VHDL #SystemVerilog #FPGA #HLS #RTL #Education #English
https://peertube.f-si.org/videos/watch/d36f3f63-fad0-4334-b7b9-82f4be9c89ef

@[email protected] asked

module my_code #( parameter int WIDTH = 640, parameter int HEIGHT = 480, parameter int CONSOLE_COLUMNS = WIDTH / 8, parameter int CONSOLE_ROWS = HEIGHT / 8 )( input logic clk, input logic rst, input int px, input int py, input logic hsync, input logic vsync, input int col, input int row, output int char, output logic [23:0] foreground_color, output logic [23:0] background_color ); logic [31:0] frame_counter = '0; logic old_vsync = '0; logic [7:0] red, green, blue; always_comb begin red = 8'(col * 4); green = 8'(py); blue = frame_counter[7:0]; background_color = {red, green, blue}; foreground_color = '1; char = 0; end always_ff @(posedge clk) begin if (vsync == 1'b0 && old_vsync == 1'b1) begin frame_counter <= frame_counter + 1; end old_vsync <= vsync; end endmodule

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB821242883.4% TRELLIS_FF142242880.6% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp40.55 MHz25 MHz $glbnet$clkt284.41 MHz250 MHz
Code

module my_code #( parameter int WIDTH = 640, parameter int HEIGHT = 480, parameter int CONSOLE_COLUMNS = WIDTH / 8, parameter int CONSOLE_ROWS = HEIGHT / 8 )( input logic clk, input logic rst, input int px, input int py, input logic hsync, input logic vsync, input int col, input int row, output int char, output logic [23:0] foreground_color, output logic [23:0] background_color ); logic [31:0] frame_counter = '0; logic old_vsync = '0; logic [7:0] red, green, blue; always_comb begin red = 8'(col * 4); green = 8'(py); blue = frame_counter[7:0]; background_color = {red, green, blue}; foreground_color = '1; char = 0; end always_ff @(posedge clk) begin if (vsync == 1'b0 && old_vsync == 1'b1) begin frame_counter <= frame_counter + 1; end old_vsync <= vsync; end endmodule

#FPGA #Icepi-Zero #HDL #SystemVerilog

@[email protected] asked

module my_code #( parameter int WIDTH = 640, parameter int HEIGHT = 480, parameter int CONSOLE_COLUMNS = WIDTH / 8, parameter int CONSOLE_ROWS = HEIGHT / 8 )( input logic clk, input logic rst, input int px, input int py, input logic hsync, input logic vsync, input int col, input int row, output int char, output logic [23:0] foreground_color, output logic [23:0] background_color ); logic [31:0] frame_counter = '0; logic old_vsync = '0; logic [7:0] wave_offset; logic [7:0] pattern_select; logic [7:0] hue_shift; // Create animated wave pattern for background assign wave_offset = frame_counter[7:0] + col; // Cycle through different pattern types assign pattern_select = frame_counter[10:8]; // Hue rotation effect assign hue_shift = frame_counter[15:8]; always_comb begin logic [7:0] red, green, blue; logic [7:0] char_value; logic [7:0] pattern_output; // Create cute animated pattern based on row and column case(pattern_select) 3'b000: pattern_output = (row + col) ^ wave_offset; // Diagonal stripes 3'b001: pattern_output = row * col + frame_counter[7:0]; // Grid pattern 3'b010: pattern_output = ((row ^ col) << 1) + hue_shift; // XOR pattern default: pattern_output = (row + frame_counter[7:0]) ^ col; // Animated checkerboard endcase // RGB color cycling with pattern red = pattern_output + hue_shift; green = pattern_output + (hue_shift >> 1); blue = pattern_output - hue_shift; background_color = {red, green, blue}; // Character selection creates a cute animation char_value = ((row * 13 + col * 7) + frame_counter[9:0]) % 256; // Display cute characters: stars, diamonds, hearts, etc. if (char_value < 64) char = 42; // '*' - star else if (char_value < 128) char = 43; // '+' - plus else if (char_value < 192) char = 46; // '.' - dot else char = 35; // '#' - hash // Foreground color inverts based on background brightness if ((red + green + blue) > 12'h600) foreground_color = 24'h000000; // Black text on bright background else foreground_color = 24'hFFFFFF; // White text on dark background end always_ff @(posedge clk) begin if (rst) begin frame_counter <= '0; old_vsync <= '0; end else begin // Increment frame counter on vsync falling edge if (vsync == 1'b0 && old_vsync == 1'b1) begin frame_counter <= frame_counter + 1; end old_vsync <= vsync; end end endmodule

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% MULT18X18D32810.7% TRELLIS_COMB1107242884.6% TRELLIS_FF152242880.6% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp40.55 MHz25 MHz $glbnet$clkt307.69 MHz250 MHz
Code

module my_code #( parameter int WIDTH = 640, parameter int HEIGHT = 480, parameter int CONSOLE_COLUMNS = WIDTH / 8, parameter int CONSOLE_ROWS = HEIGHT / 8 )( input logic clk, input logic rst, input int px, input int py, input logic hsync, input logic vsync, input int col, input int row, output int char, output logic [23:0] foreground_color, output logic [23:0] background_color ); logic [31:0] frame_counter = '0; logic old_vsync = '0; logic [7:0] wave_offset; logic [7:0] pattern_select; logic [7:0] hue_shift; // Create animated wave pattern for background assign wave_offset = frame_counter[7:0] + col; // Cycle through different pattern types assign pattern_select = frame_counter[10:8]; // Hue rotation effect assign hue_shift = frame_counter[15:8]; always_comb begin logic [7:0] red, green, blue; logic [7:0] char_value; logic [7:0] pattern_output; // Create cute animated pattern based on row and column case(pattern_select) 3'b000: pattern_output = (row + col) ^ wave_offset; // Diagonal stripes 3'b001: pattern_output = row * col + frame_counter[7:0]; // Grid pattern 3'b010: pattern_output = ((row ^ col) << 1) + hue_shift; // XOR pattern default: pattern_output = (row + frame_counter[7:0]) ^ col; // Animated checkerboard endcase // RGB color cycling with pattern red = pattern_output + hue_shift; green = pattern_output + (hue_shift >> 1); blue = pattern_output - hue_shift; background_color = {red, green, blue}; // Character selection creates a cute animation char_value = ((row * 13 + col * 7) + frame_counter[9:0]) % 256; // Display cute characters: stars, diamonds, hearts, etc. if (char_value < 64) char = 42; // '*' - star else if (char_value < 128) char = 43; // '+' - plus else if (char_value < 192) char = 46; // '.' - dot else char = 35; // '#' - hash // Foreground color inverts based on background brightness if ((red + green + blue) > 12'h600) foreground_color = 24'h000000; // Black text on bright background else foreground_color = 24'hFFFFFF; // White text on dark background end always_ff @(posedge clk) begin if (rst) begin frame_counter <= '0; old_vsync <= '0; end else begin // Increment frame counter on vsync falling edge if (vsync == 1'b0 && old_vsync == 1'b1) begin frame_counter <= frame_counter + 1; end old_vsync <= vsync; end end endmodule

#FPGA #Icepi-Zero #HDL #SystemVerilog

@[email protected] asked

module my_code #( parameter int WIDTH = 640, parameter int HEIGHT = 480, parameter int CONSOLE_COLUMNS = WIDTH / 8, parameter int CONSOLE_ROWS = HEIGHT / 8 )( input logic clk, input logic rst, input int px, input int py, input logic hsync, input logic vsync, input int col, input int row, output int char, output logic [23:0] foreground_color, output logic [23:0] background_color ); // A "heartbeat" counter that ticks every frame to create a subtle animation effect logic [31:0] frame_counter = '0; logic old_vsync = '0; // Separate RGB channels for more creative color mixing logic [7:0] r_val, g_val, b_val; // A "mood" counter that cycles through different color palettes based on row position logic [31:0] mood_counter = '0; always_comb begin // Calculate dynamic colors based on input coordinates and frame time // Red channel: influenced by column position and frame counter low bits r_val = 8'({col[2:0], frame_counter[7:0][3:0]}); // Green channel: influenced by row position and mood counter g_val = 8'({row[1:0], mood_counter[15:14]}); // Blue channel: a mix of all inputs for a "glow" effect b_val = 8'(frame_counter[7:0][6:4] ^ row[2:0]); background_color = {r_val, g_val, b_val}; // Foreground is always white with a slight tint based on frame counter foreground_color = '1; if (frame_counter[31:28]) begin foreground_color = 24'b0000_0000_0000_0000_0000_0001; // Pure white end else begin foreground_color = 'hFFFFFF; // Light cyan tint end char = row + col; end always_ff @(posedge clk) begin if (rst == 1'b1) begin frame_counter <= '0; mood_counter <= '0; end else if (vsync == 1'b0 && old_vsync == 1'b1) begin // Increment counters on every new video frame frame_counter <= frame_counter + 1; mood_counter <= mood_counter + 1; end old_vsync <= vsync; end endmodule

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB1245242885.1% TRELLIS_FF175242880.7% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp39.97 MHz25 MHz $glbnet$clkt293.51 MHz250 MHz
Code

module my_code #( parameter int WIDTH = 640, parameter int HEIGHT = 480, parameter int CONSOLE_COLUMNS = WIDTH / 8, parameter int CONSOLE_ROWS = HEIGHT / 8 )( input logic clk, input logic rst, input int px, input int py, input logic hsync, input logic vsync, input int col, input int row, output int char, output logic [23:0] foreground_color, output logic [23:0] background_color ); // A "heartbeat" counter that ticks every frame to create a subtle animation effect logic [31:0] frame_counter = '0; logic old_vsync = '0; // Separate RGB channels for more creative color mixing logic [7:0] r_val, g_val, b_val; // A "mood" counter that cycles through different color palettes based on row position logic [31:0] mood_counter = '0; always_comb begin // Calculate dynamic colors based on input coordinates and frame time // Red channel: influenced by column position and frame counter low bits r_val = 8'({col[2:0], frame_counter[7:0][3:0]}); // Green channel: influenced by row position and mood counter g_val = 8'({row[1:0], mood_counter[15:14]}); // Blue channel: a mix of all inputs for a "glow" effect b_val = 8'(frame_counter[7:0][6:4] ^ row[2:0]); background_color = {r_val, g_val, b_val}; // Foreground is always white with a slight tint based on frame counter foreground_color = '1; if (frame_counter[31:28]) begin foreground_color = 24'b0000_0000_0000_0000_0000_0001; // Pure white end else begin foreground_color = 'hFFFFFF; // Light cyan tint end char = row + col; end always_ff @(posedge clk) begin if (rst == 1'b1) begin frame_counter <= '0; mood_counter <= '0; end else if (vsync == 1'b0 && old_vsync == 1'b1) begin // Increment counters on every new video frame frame_counter <= frame_counter + 1; mood_counter <= mood_counter + 1; end old_vsync <= vsync; end endmodule

#FPGA #Icepi-Zero #HDL #SystemVerilog