Mastodawn

Merged in the #ilo in #webassembly (http://fossils.retroforth.org:8000/ilo/info/0d2723f9408770fd) and the current #ilo in #vhdl work (http://fossils.retroforth.org:8000/ilo/info/95e971fd442d4008) to the Fossil repository. They'll hit the git mirrors later today.

konilo: Check-in [0d2723f940]

crc 1d ago

I'm continuing to work on my #ilo in #vhdl. I've reduced the LUT count from a generic synthesis from 9k to 4.6k by changing the handling of the stacks, and some further work on the overall instruction implementations.

I've also started working towards board support (currently looking at Cmod A7-35T & Icepi Zero boards), though I don't yet have any actual hardware to test on.

crc 4d ago

Not fully tested yet, but after a bit of help, I've managed to get the #ilo in #vhdl to progress far enough that I can interact with a standard konilo rom on it using ghdl for simulation. I'm routing simulated serial i/o to a pair of fifo's and using a little python wrapper to communicate with it.

An initial synthesis report: https://gist.github.com/crcx/46408c86a5a0321fe5376aa574b55c8b

A short demo video at https://asciinema.org/a/3U0UXv7NcZBF5xX9

The initial code is at http://charles.childe.rs/temp/ilo-ghdl.tar.gz

This is not in the repository yet. I want to do further testing and add some notes on it before I commit it.

If anyone takes a look, I'd appreciate any feedback. I'm not a hardware guy, so this is not going to be a good example of VHDL and has been a big learning experience so far.

gist:46408c86a5a0321fe5376aa574b55c8b

GitHub Gist: instantly share code, notes, and snippets.

Gist

Open Source Electronics Wiki Jun 18

Which Verilog TMDS encoding library do you recommend that I use on the Ice Pi Zero? Here is my review of the options.

https://wiki.pythonlinks.info/dvi-rtl-libraries

#Verilog #VHDL #tMDS #IcePiZero

DVI RTL Libraries

This article lists and evaluates the various libraries for driving DVI output from FPGAs. My goal is to help both of us choose the right library for our applications.

Icepi Zero Bot Jun 11

@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)) xor std_logic_vector(resize(frame_counter, 8)); green <= std_logic_vector(to_unsigned(py, 8)) xor std_logic_vector(to_unsigned(px, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

Success!

UART Output

... [TRUNCATED] ...
llo Fediverse on UART!
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He

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1178242884.9%TRELLIS_FF176242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp40.37 MHz25 MHz$glbnet$clkt285.63 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8)) xor std_logic_vector(resize(frame_counter, 8));
    green <= std_logic_vector(to_unsigned(py, 8)) xor std_logic_vector(to_unsigned(px, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

Icepi Zero Bot Jun 11

@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); signal example_text : string(1 to 13) := "temp = ???? C"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; type temperature_map_t is array (0 to 63) of string(1 to 4); constant temperature_map : temperature_map_t := ( 0 => " -58", 1 => " -56", 2 => " -54", 3 => " -52", 4 => " -45", 5 => " -44", 6 => " -43", 7 => " -42", 8 => " -41", 9 => " -40", 10 => "- 39", 11 => "- 38", 12 => "- 37", 13 => "- 36", 14 => "- 30", 15 => "- 20", 16 => "- 10", 17 => "- 4", 18 => " 0", 19 => "+ 4", 20 => "+ 10", 21 => "+ 21", 22 => "+ 22", 23 => "+ 23", 24 => "+ 24", 25 => "+ 25", 26 => "+ 26", 27 => "+ 27", 28 => "+ 28", 29 => "+ 29", 30 => "+ 40", 31 => "+ 50", 32 => "+ 60", 33 => "+ 70", 34 => "+ 76", 35 => "+ 80", 36 => "+ 81", 37 => "+ 82", 38 => "+ 83", 39 => "+ 84", 40 => "+ 85", 41 => "+ 86", 42 => "+ 87", 43 => "+ 88", 44 => "+ 89", 45 => "+ 95", 46 => "+ 96", 47 => "+ 97", 48 => "+ 98", 49 => "+ 99", 50 => "+100", 51 => "+101", 52 => "+102", 53 => "+103", 54 => "+104", 55 => "+105", 56 => "+106", 57 => "+107", 58 => "+108", 59 => "+116", 60 => "+120", 61 => "+124", 62 => "+128", 63 => "+132" ); component DTR is port ( STARTPULSE : in std_logic; DTROUT7 : out std_logic; DTROUT6 : out std_logic; DTROUT5 : out std_logic; DTROUT4 : out std_logic; DTROUT3 : out std_logic; DTROUT2 : out std_logic; DTROUT1 : out std_logic; DTROUT0 : out std_logic ); end component; signal temp : unsigned(5 downto 0) := (others => '0'); signal startpulse : std_logic := '0'; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); dtr_inst: DTR port map ( STARTPULSE => startpulse, DTROUT7 => open, DTROUT6 => open, DTROUT5 => temp(5), DTROUT4 => temp(4), DTROUT3 => temp(3), DTROUT2 => temp(2), DTROUT1 => temp(1), DTROUT0 => temp(0) ); example_text(8 to 11) <= temperature_map(to_integer(temp)); process(clk) variable old_vsync : std_logic := '0'; begin if rising_edge(clk) then startpulse <= '0'; if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; startpulse <= '1'; end if; old_vsync := vsync; end if; end process; end architecture;

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%DTR11100.0%EHXPLLL1250.0%TRELLIS_COMB1238242885.1%TRELLIS_FF158242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp40.71 MHz25 MHz$glbnet$clkt319.69 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    signal example_text : string(1 to 13) := "temp = ???? C";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    type temperature_map_t is array (0 to 63) of string(1 to 4);
    constant temperature_map : temperature_map_t := (
        0 =>  " -58",
        1 =>  " -56",
        2 =>  " -54",
        3 =>  " -52",
        4 =>  " -45",
        5 =>  " -44",
        6 =>  " -43",
        7 =>  " -42",
        8 =>  " -41",
        9 =>  " -40",
        10 => "- 39",
        11 => "- 38",
        12 => "- 37",
        13 => "- 36",
        14 => "- 30",
        15 => "- 20",
        16 => "- 10",
        17 => "-  4",
        18 => "   0",
        19 => "+  4",
        20 => "+ 10",
        21 => "+ 21",
        22 => "+ 22",
        23 => "+ 23",
        24 => "+ 24",
        25 => "+ 25",
        26 => "+ 26",
        27 => "+ 27",
        28 => "+ 28",
        29 => "+ 29",
        30 => "+ 40",
        31 => "+ 50",
        32 => "+ 60",
        33 => "+ 70",
        34 => "+ 76",
        35 => "+ 80",
        36 => "+ 81",
        37 => "+ 82",
        38 => "+ 83",
        39 => "+ 84",
        40 => "+ 85",
        41 => "+ 86",
        42 => "+ 87",
        43 => "+ 88",
        44 => "+ 89",
        45 => "+ 95",
        46 => "+ 96",
        47 => "+ 97",
        48 => "+ 98",
        49 => "+ 99",
        50 => "+100",
        51 => "+101",
        52 => "+102",
        53 => "+103",
        54 => "+104",
        55 => "+105",
        56 => "+106",
        57 => "+107",
        58 => "+108",
        59 => "+116",
        60 => "+120",
        61 => "+124",
        62 => "+128",
        63 => "+132"
    );

    component DTR is
        port (
            STARTPULSE : in std_logic;
            DTROUT7 : out std_logic;
            DTROUT6 : out std_logic;
            DTROUT5 : out std_logic;
            DTROUT4 : out std_logic;
            DTROUT3 : out std_logic;
            DTROUT2 : out std_logic;
            DTROUT1 : out std_logic;
            DTROUT0 : out std_logic
        );
    end component;
    signal temp : unsigned(5 downto 0) := (others => '0');
    signal startpulse : std_logic := '0';
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    dtr_inst: DTR
        port map (
            STARTPULSE => startpulse,
            DTROUT7 => open,
            DTROUT6 => open,
            DTROUT5 => temp(5),
            DTROUT4 => temp(4),
            DTROUT3 => temp(3),
            DTROUT2 => temp(2),
            DTROUT1 => temp(1),
            DTROUT0 => temp(0)
        );
    example_text(8 to 11) <= temperature_map(to_integer(temp));

    process(clk)
        variable old_vsync : std_logic := '0';
    begin
        if rising_edge(clk) then
            startpulse <= '0';
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
                startpulse <= '1';
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

Icepi Zero Bot Jun 11

@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is constant IMAGE_WIDTH : integer := 32; constant IMAGE_HEIGHT : integer := 25; type image_type is array (IMAGE_HEIGHT*IMAGE_WIDTH*12-1 downto 0) of std_logic; constant image : image_type := x"00000000000000000000000000000000000000000000000123400000000000111200000000000000000000000000000000000000000000000000000000000000000000000000044645700000000022344700000000000000000000000000000000000000000000000000000000000000000000000000056845700100000033556800100000000000000000000000000000000000000000000000000000000000000000000000145744611100000034555800000000000000000000000000000000000000000000000000000000000000000000000000033533522423422444633500011075364300000000000000000000000000000000000000000000000000000000000000012334568979b457345123000964eb7da73211100000000000000000000000000000000000000000000000000000000003448abaddadd8ab79a578211c86fa7fa7c86c867430000000000000000000000000000000000000000000000000000005788bcaddadd8ab8ab689777eddebae96f96f9696400000000000000000000000000000000000000000000000011122289a89a9cdadd9aaabb79a777cccca9d85d85b643100000000000000000000000000000000000000000000002217657659aaabcacdaddbcdbcd7ab456888866754532210000000000000000000000000000000000000000000000000332765765789acdadeaddadd9cd58923444522200000011133333300000000000000000000000000000000000000000011154377688978a9bcacd9cc7ac7ad347000000433999bbbddcaaa0000000000000000000000000000000000000000001223443452235679bcabc9bc9ab68b46a124444bbbeddeedddd7770000000000000000000000000000000000000005679bd7ac78b769678cdddeecddacc7ae47a567888cccdddccc8881110000000000001110000000000003333331111115668ab69b89c88a668bcddeecee9bc67b56a99bcccaaa999555111111000000555aaacccbbb333222777eeeeeeccccdddddbbb445abceefeffeeeeeeeeedeedeeddebbcbbcdddeeebbbbbbcccbbb666dddeffdeffffdddccceeedefbdfeffdefbeffff999cccdefadfbefcefdefcefbefbefdeeeefadfbefffffffcefeffcccfffadf4cfdeffffdefeffbdf4cfadf3cf3cfbefeeedddbdf3bf3cf4cf6cf3cf5cf4cf7cfcef4cf4cfdefdff5cfbefdddcccdef3cf9dfdef4cfbdf9df4cf7cf3cf4cf6cfefffffadf4cfadfcef9df4cfdefadf2bf9df4cf3cf8cfdef4cfcefccd888fff9df3bf9cf3af7bf6af5af5af7bfadf3afadffff8cf2bf3bfcefadf3bfadf8cf3bfbdf4bf9cf5bf7bf3afdefbbb444ddddef48f37f47f37f26f58f37f57fbcf89f47fcdf79f79fbdfeffbcf38f6af49f38fabf48fbcf9af27f37feefaaa000aaafff79f37fbcf57f37f8af37f68fccfddf57f89f58f9bfffffffbcf37fddfddf47f57f47fbcfddf37f47ffff999000344eeeddfbcfeffddfcdfdefabfeefffffffdefeefddfeefddeccdddf9afeeffffddfddfddfeeffffbcfbcffff77800000099aeeeeeeddeddeddeeeeeefdee89abbcddeccdddddde99a99aeeffffeefdddeeeddeddeccdcddeeefffddd45600000022456866845745745755767956822423544723534645723433477978a679446567457446346346568679558112"; constant SPEED : integer := 8; signal position_x : integer range -SPEED to WIDTH + SPEED := 0; signal position_y : integer range -SPEED to HEIGHT + SPEED := 0; signal random_bit : std_logic := '0'; signal color : std_logic_vector(23 downto 0) := x"FFFFFF"; component OSCG is generic ( DIV : integer := 128 ); port ( OSC : out std_logic ); end component; signal pos : integer range 0 to IMAGE_HEIGHT*IMAGE_WIDTH*12; signal r, g, b : std_logic_vector(3 downto 0); begin char <= 0; pos <= IMAGE_HEIGHT*IMAGE_WIDTH*12 - 1 - 12*(py - position_y)*(px - position_x); r <= image(pos) & image(pos - 1) & image(pos - 2) & image(pos - 3); g <= image(pos - 4) & image(pos - 5) & image(pos - 6) & image(pos - 7); b <= image(pos - 8) & image(pos - 9) & image(pos - 10) & image(pos - 11); background_color <= r & r & g & g & b & b when px >= position_x and px < position_x + IMAGE_WIDTH and py >= position_y and py < position_y + IMAGE_HEIGHT else x"000000"; foreground_color <= (others => '1'); rng : OSCG port map ( OSC => random_bit ); process(clk) variable old_vsync : std_logic := '0'; variable speed_x : integer range -SPEED to SPEED := SPEED; variable speed_y : integer range -SPEED to SPEED := SPEED; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then if position_x + speed_x + IMAGE_WIDTH >= WIDTH then speed_x := -SPEED; position_x <= WIDTH - IMAGE_WIDTH - 1; color <= color(22 downto 0) & random_bit; elsif position_x + speed_x < 0 then speed_x := SPEED; position_x <= 0; color <= color(22 downto 0) & random_bit; else position_x <= position_x + speed_x; end if; if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then speed_y := -SPEED; position_y <= HEIGHT - IMAGE_HEIGHT - 1; color <= color(22 downto 0) & random_bit; elsif position_y + speed_y < 0 then speed_y := SPEED; position_y <= 0; color <= color(22 downto 0) & random_bit; else position_y <= position_y + speed_y; end if; end if; old_vsync := vsync; end if; end process; end architecture;

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%MULT18X18D2287.1%TRELLIS_COMB29372428812.1%TRELLIS_FF160242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp30.03 MHz25 MHz$glbnet$clkt341.41 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    constant IMAGE_WIDTH : integer := 32;
    constant IMAGE_HEIGHT : integer := 25;

    type image_type is array (IMAGE_HEIGHT*IMAGE_WIDTH*12-1 downto 0) of std_logic;
    constant image : image_type := x"00000000000000000000000000000000000000000000000123400000000000111200000000000000000000000000000000000000000000000000000000000000000000000000044645700000000022344700000000000000000000000000000000000000000000000000000000000000000000000000056845700100000033556800100000000000000000000000000000000000000000000000000000000000000000000000145744611100000034555800000000000000000000000000000000000000000000000000000000000000000000000000033533522423422444633500011075364300000000000000000000000000000000000000000000000000000000000000012334568979b457345123000964eb7da73211100000000000000000000000000000000000000000000000000000000003448abaddadd8ab79a578211c86fa7fa7c86c867430000000000000000000000000000000000000000000000000000005788bcaddadd8ab8ab689777eddebae96f96f9696400000000000000000000000000000000000000000000000011122289a89a9cdadd9aaabb79a777cccca9d85d85b643100000000000000000000000000000000000000000000002217657659aaabcacdaddbcdbcd7ab456888866754532210000000000000000000000000000000000000000000000000332765765789acdadeaddadd9cd58923444522200000011133333300000000000000000000000000000000000000000011154377688978a9bcacd9cc7ac7ad347000000433999bbbddcaaa0000000000000000000000000000000000000000001223443452235679bcabc9bc9ab68b46a124444bbbeddeedddd7770000000000000000000000000000000000000005679bd7ac78b769678cdddeecddacc7ae47a567888cccdddccc8881110000000000001110000000000003333331111115668ab69b89c88a668bcddeecee9bc67b56a99bcccaaa999555111111000000555aaacccbbb333222777eeeeeeccccdddddbbb445abceefeffeeeeeeeeedeedeeddebbcbbcdddeeebbbbbbcccbbb666dddeffdeffffdddccceeedefbdfeffdefbeffff999cccdefadfbefcefdefcefbefbefdeeeefadfbefffffffcefeffcccfffadf4cfdeffffdefeffbdf4cfadf3cf3cfbefeeedddbdf3bf3cf4cf6cf3cf5cf4cf7cfcef4cf4cfdefdff5cfbefdddcccdef3cf9dfdef4cfbdf9df4cf7cf3cf4cf6cfefffffadf4cfadfcef9df4cfdefadf2bf9df4cf3cf8cfdef4cfcefccd888fff9df3bf9cf3af7bf6af5af5af7bfadf3afadffff8cf2bf3bfcefadf3bfadf8cf3bfbdf4bf9cf5bf7bf3afdefbbb444ddddef48f37f47f37f26f58f37f57fbcf89f47fcdf79f79fbdfeffbcf38f6af49f38fabf48fbcf9af27f37feefaaa000aaafff79f37fbcf57f37f8af37f68fccfddf57f89f58f9bfffffffbcf37fddfddf47f57f47fbcfddf37f47ffff999000344eeeddfbcfeffddfcdfdefabfeefffffffdefeefddfeefddeccdddf9afeeffffddfddfddfeeffffbcfbcffff77800000099aeeeeeeddeddeddeeeeeefdee89abbcddeccdddddde99a99aeeffffeefdddeeeddeddeccdcddeeefffddd45600000022456866845745745755767956822423544723534645723433477978a679446567457446346346568679558112";

    constant SPEED : integer := 8;

    signal position_x : integer range -SPEED to WIDTH + SPEED := 0;
    signal position_y : integer range -SPEED to HEIGHT + SPEED := 0;

    signal random_bit : std_logic := '0';
    signal color : std_logic_vector(23 downto 0) := x"FFFFFF";

    component OSCG is
        generic (
            DIV : integer := 128
        );
        port (
            OSC : out std_logic
        );
    end component;

    signal pos : integer range 0 to IMAGE_HEIGHT*IMAGE_WIDTH*12;
    signal r, g, b : std_logic_vector(3 downto 0);
begin
    char <= 0;

    pos <= IMAGE_HEIGHT*IMAGE_WIDTH*12 - 1 - 12*(py - position_y)*(px - position_x);
    r <= image(pos) & image(pos - 1) & image(pos - 2) & image(pos - 3);
    g <= image(pos - 4) & image(pos - 5) & image(pos - 6) & image(pos - 7);
    b <= image(pos - 8) & image(pos - 9) & image(pos - 10) & image(pos - 11);

    background_color <= r & r & g & g & b & b
        when
            px >= position_x and px < position_x + IMAGE_WIDTH and
            py >= position_y and py < position_y + IMAGE_HEIGHT
        else x"000000";
    foreground_color <= (others => '1');

    rng : OSCG port map (
        OSC => random_bit
    );

    process(clk)
        variable old_vsync : std_logic := '0';
        variable speed_x : integer range -SPEED to SPEED := SPEED;
        variable speed_y : integer range -SPEED to SPEED := SPEED;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                if position_x + speed_x + IMAGE_WIDTH >= WIDTH then
                    speed_x := -SPEED;
                    position_x <= WIDTH - IMAGE_WIDTH - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_x + speed_x < 0 then
                    speed_x := SPEED;
                    position_x <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_x <= position_x + speed_x;
                end if;

                if position_y + speed_y + IMAGE_HEIGHT >= HEIGHT then
                    speed_y := -SPEED;
                    position_y <= HEIGHT - IMAGE_HEIGHT - 1;

                    color <= color(22 downto 0) & random_bit;
                elsif position_y + speed_y < 0 then
                    speed_y := SPEED;
                    position_y <= 0;

                    color <= color(22 downto 0) & random_bit;
                else
                    position_y <= position_y + speed_y;
                end if;
            end if;
            old_vsync := vsync;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

Icepi Zero Bot Jun 6

@[email protected]

@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

Success!

UART Output

... [TRUNCATED] ...
T!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
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Hello Fediverse on UART!
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Hello Fediverse on UART!
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Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UART!
Hello Fediverse on UAR

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL

Show thread

Pete Bleackley May 26

@adrian Your post doesn't mention #VHDL at all. As far as I remember from my brief use of it about 20 years ago, it doesn't require #Verilog as an intermediate stage. Can you comment on it?

Icepi Zero Bot May 24

@[email protected]

@[email protected] asked

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity my_code is generic( WIDTH : integer := 640; HEIGHT : integer := 480; CONSOLE_COLUMNS : integer := WIDTH / 8; CONSOLE_ROWS : integer := HEIGHT / 8 ); port( clk : in std_logic; rst : in std_logic; px : in integer range 0 to WIDTH - 1; py : in integer range 0 to HEIGHT - 1; hsync : in std_logic; vsync : in std_logic; col : in integer range 0 to CONSOLE_COLUMNS - 1; row : in integer range 0 to CONSOLE_ROWS - 1; char : out integer range 0 to 127 := 0; foreground_color : out std_logic_vector(23 downto 0) := (others => '0'); background_color : out std_logic_vector(23 downto 0) := (others => '1'); uart_data : out std_logic_vector(7 downto 0) := (others => '0'); uart_ready : in std_logic; uart_valid : out std_logic := '0' ); end my_code; architecture rtl of my_code is alias red : std_logic_vector(7 downto 0) is background_color(23 downto 16); alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8); alias blue : std_logic_vector(7 downto 0) is background_color(7 downto 0); signal frame_counter : unsigned(31 downto 0) := (others => '0'); constant example_text : string := "Hello Fediverse! <3"; constant example_text_row : integer := 15; constant example_text_col : integer := 15; constant uart_text : string := "Hello Fediverse on UART!" & LF; begin char <= character'pos(example_text(col + 1 - example_text_col)) when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0; red <= std_logic_vector(to_unsigned(col*4, 8)); green <= std_logic_vector(to_unsigned(py, 8)); blue <= std_logic_vector(resize(frame_counter, 8)); foreground_color <= (others => '1'); process(clk) variable old_vsync : std_logic := '0'; variable uart_counter : integer range uart_text'range := 1; begin if rising_edge(clk) then if vsync = '0' and old_vsync = '1' then frame_counter <= frame_counter + 1; end if; old_vsync := vsync; uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8)); uart_valid <= '1'; if uart_ready = '1' and uart_valid = '1' then if uart_counter < uart_text'length then uart_counter := uart_counter + 1; else uart_counter := 1; end if; end if; end if; end process; end architecture;

Success!

UART Output

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UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1171242884.8%TRELLIS_FF177242880.7%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.04 MHz25 MHz$glbnet$clkt345.18 MHz250 MHz
Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_code is
    generic(
        WIDTH : integer := 640;
        HEIGHT : integer := 480;
        CONSOLE_COLUMNS : integer := WIDTH / 8;
        CONSOLE_ROWS : integer := HEIGHT / 8
    );
    port(
        clk : in std_logic;
        rst : in std_logic;

        px : in integer range 0 to WIDTH - 1;
        py : in integer range 0 to HEIGHT - 1;
        hsync : in std_logic;
        vsync : in std_logic;

        col : in integer range 0 to CONSOLE_COLUMNS - 1;
        row : in integer range 0 to CONSOLE_ROWS - 1;

        char : out integer range 0 to 127 := 0;
        foreground_color : out std_logic_vector(23 downto 0) := (others => '0');
        background_color : out std_logic_vector(23 downto 0) := (others => '1');

        uart_data : out std_logic_vector(7 downto 0) := (others => '0');
        uart_ready : in std_logic;
        uart_valid : out std_logic := '0'
    );
end my_code;

architecture rtl of my_code is
    alias red   : std_logic_vector(7 downto 0) is background_color(23 downto 16);
    alias green : std_logic_vector(7 downto 0) is background_color(15 downto 8);
    alias blue  : std_logic_vector(7 downto 0) is background_color(7 downto 0);

    signal frame_counter : unsigned(31 downto 0) := (others => '0');

    constant example_text : string := "Hello Fediverse! <3";
    constant example_text_row : integer := 15;
    constant example_text_col : integer := 15;

    constant uart_text : string := "Hello Fediverse on UART!" & LF;
begin
    char <= character'pos(example_text(col + 1 - example_text_col))
        when col >= example_text_col and col < example_text'length + example_text_col and row = example_text_row else 0;

    red   <= std_logic_vector(to_unsigned(col*4, 8));
    green <= std_logic_vector(to_unsigned(py, 8));
    blue  <= std_logic_vector(resize(frame_counter, 8));

    foreground_color <= (others => '1');

    process(clk)
        variable old_vsync : std_logic := '0';

        variable uart_counter : integer range uart_text'range := 1;
    begin
        if rising_edge(clk) then
            if vsync = '0' and old_vsync = '1' then
                frame_counter <= frame_counter + 1;
            end if;
            old_vsync := vsync;

            uart_data <= std_logic_vector(to_unsigned(character'pos(uart_text(uart_counter)), 8));
            uart_valid <= '1';
            if uart_ready = '1' and uart_valid = '1' then
                if uart_counter < uart_text'length then
                    uart_counter := uart_counter + 1;
                else
                    uart_counter := 1;
                end if;
            end if;
        end if;
    end process;
end architecture;

#FPGA #Icepi-Zero #HDL #VHDL