@[email protected] asked

module my_code #( param WIDTH: p32 = 640, param HEIGHT: p32 = 480, param CONSOLE_COLUMNS: p32 = WIDTH / 8, param CONSOLE_ROWS: p32 = HEIGHT / 8 ) ( clk: input clock, rst: input reset, px: input u32, py: input u32, hsync: input logic, vsync: input logic, col: input u32, row: input u32, char: output u32, foreground_color: output logic<24>, background_color: output logic<24>, uart_data: output logic<8>, uart_ready: input logic, uart_valid: output logic ) { var frame_counter: u32; var old_vsync: logic; var red: logic<8>; var green: logic<8>; var blue: logic<8>; always_comb { red = (col * 4) as u8; green = py as u8; blue = frame_counter as u8; background_color = {red, green, blue}; foreground_color = 24'hff_ff_ff; char = 0; if(row == 10) { if(col == 5) { char = 8'h56; } if(col == 6) { char = 8'h65; } if(col == 7) { char = 8'h72; } if(col == 8) { char = 8'h79; } if(col == 9) { char = 8'h6c; } } uart_data = 0; uart_valid = 0; } always_ff (clk, rst) { if_reset { frame_counter = 0; old_vsync = 0; } else { if(!vsync && old_vsync) { frame_counter = frame_counter + 1; } old_vsync = vsync; } } }

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1024242884.2%TRELLIS_FF157242880.6%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.77 MHz25 MHz$glbnet$clkt321.34 MHz250 MHz
Code

module my_code #( param WIDTH: p32 = 640, param HEIGHT: p32 = 480, param CONSOLE_COLUMNS: p32 = WIDTH / 8, param CONSOLE_ROWS: p32 = HEIGHT / 8 ) ( clk: input clock, rst: input reset, px: input u32, py: input u32, hsync: input logic, vsync: input logic, col: input u32, row: input u32, char: output u32, foreground_color: output logic<24>, background_color: output logic<24>, uart_data: output logic<8>, uart_ready: input logic, uart_valid: output logic ) { var frame_counter: u32; var old_vsync: logic; var red: logic<8>; var green: logic<8>; var blue: logic<8>; always_comb { red = (col * 4) as u8; green = py as u8; blue = frame_counter as u8; background_color = {red, green, blue}; foreground_color = 24'hff_ff_ff; char = 0; if(row == 10) { if(col == 5) { char = 8'h56; } if(col == 6) { char = 8'h65; } if(col == 7) { char = 8'h72; } if(col == 8) { char = 8'h79; } if(col == 9) { char = 8'h6c; } } uart_data = 0; uart_valid = 0; } always_ff (clk, rst) { if_reset { frame_counter = 0; old_vsync = 0; } else { if(!vsync && old_vsync) { frame_counter = frame_counter + 1; } old_vsync = vsync; } } }

#FPGA #Icepi-Zero #HDL #Veryl

@[email protected]

@[email protected] asked

module my_code #( param WIDTH: u32 = 640, param HEIGHT: u32 = 480, param CONSOLE_COLUMNS: u32 = WIDTH / 8, param CONSOLE_ROWS: u32 = HEIGHT / 8 ) ( clk: input clock, rst: input reset, px: input u32, py: input u32, hsync: input logic, vsync: input logic, col: input u32, row: input u32, char: output u32, foreground_color: output logic<24>, background_color: output logic<24>, uart_data: output logic<8>, uart_ready: input logic, uart_valid: output logic ) { var frame_counter: u32; var old_vsync: logic; var red: logic<8>; var green: logic<8>; var blue: logic<8>; always_comb { red = (col * 4) as u8; green = py as u8; blue = frame_counter as u8; background_color = {red, green, blue}; foreground_color = 24'hff_ff_ff; char = 0; if(row == 10) { if(col == 5) { char = 8'h56; } if(col == 6) { char = 8'h65; } if(col == 7) { char = 8'h72; } if(col == 8) { char = 8'h79; } if(col == 9) { char = 8'h6c; } } uart_data = 0; uart_valid = 0; } always_ff (clk, rst) { if_reset { frame_counter = 0; old_vsync = 0; } else { if(!vsync && old_vsync) { frame_counter = frame_counter + 1; } old_vsync = vsync; } } }

Success!

UART Output

UtilizationCellUsedAvailableUsageDCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB1024242884.2%TRELLIS_FF157242880.6%TRELLIS_IO111975.6%
TimingClockAchievedConstraint$glbnet$clkp39.77 MHz25 MHz$glbnet$clkt321.34 MHz250 MHz
Code

module my_code #( param WIDTH: u32 = 640, param HEIGHT: u32 = 480, param CONSOLE_COLUMNS: u32 = WIDTH / 8, param CONSOLE_ROWS: u32 = HEIGHT / 8 ) ( clk: input clock, rst: input reset, px: input u32, py: input u32, hsync: input logic, vsync: input logic, col: input u32, row: input u32, char: output u32, foreground_color: output logic<24>, background_color: output logic<24>, uart_data: output logic<8>, uart_ready: input logic, uart_valid: output logic ) { var frame_counter: u32; var old_vsync: logic; var red: logic<8>; var green: logic<8>; var blue: logic<8>; always_comb { red = (col * 4) as u8; green = py as u8; blue = frame_counter as u8; background_color = {red, green, blue}; foreground_color = 24'hff_ff_ff; char = 0; if(row == 10) { if(col == 5) { char = 8'h56; } if(col == 6) { char = 8'h65; } if(col == 7) { char = 8'h72; } if(col == 8) { char = 8'h79; } if(col == 9) { char = 8'h6c; } } uart_data = 0; uart_valid = 0; } always_ff (clk, rst) { if_reset { frame_counter = 0; old_vsync = 0; } else { if(!vsync && old_vsync) { frame_counter = frame_counter + 1; } old_vsync = vsync; } } }

#FPGA #Icepi-Zero #HDL #Veryl

@[email protected]

I am pleased to announce that @icepi-zero-bot is back up and running. 

Now inside my Kubernetes cluster on more powerful hardware, so you should hopefully see some faster synthesis times and slightly nicer videos!
I think I secured it pretty well, but if someone manages to do something naughty, please don't nom-nom all my data :pleading_face:
Also, please don't break my FPGA on purporse, oki? :3

Sadly, I still need to figure out Spade support, because I couldn't find any prebuilt arm64 binaries for it :(

So, if you want to write cool SystemVerilog/VHDL/Amaranth/Veryl code, have it run on a real FPGA and output video (no need to implement DVI yourself, dw), which is then recorded and posted, check out @icepi-zero-bot's profile! The profile description contains tons of explanations and templates.

Soon, I will hopefully add Spade support back and also implement a UART interface, so you can also output text! The support for that in the bot is already there, I just need to implement a UART transmitter in VHDL and think of a cute and easy interface.

RE: https://wafrn.jcm.re/fediverse/post/83972345-09e4-47d9-99d3-4a3885a2a198
#fedibot #FPGA #HDL #VHDL #Verilog #SystemVerilog #Amaranth #Veryl

I am happy to announce that the @icepi-zero-bot has Veryl support (it actually had it since a couple of days, but now I finally have a tiny bit of time to announce it)!
Thanks to @Tathar for the request and the help with setting things up.

RE: https://wafrn.jcm.re/fediverse/post/fb21908c-6fe6-4693-9bd9-5718b5314334
#FPGA #Icepi-Zero #fedibot #Veryl #HDL

@[email protected] asked

module my_code #( param WIDTH: u32 = 640, param HEIGHT: u32 = 480, param CONSOLE_COLUMNS: u32 = WIDTH / 8, param CONSOLE_ROWS: u32 = HEIGHT / 8 ) ( clk: input clock, rst: input reset, px: input u32, py: input u32, hsync: input logic, vsync: input logic, col: input u32, row: input u32, char: output u32, foreground_color: output logic<24>, background_color: output logic<24> ) { var frame_counter: u32; var old_vsync: logic; var red: logic<8>; var green: logic<8>; var blue: logic<8>; always_comb { red = (col * 4) as u8; green = py as u8; blue = frame_counter as u8; background_color = {red, green, blue}; foreground_color = 24'hff_ff_ff; char = 0; if(row == 10) { if(col == 5) { char = 8'h56; } if(col == 6) { char = 8'h65; } if(col == 7) { char = 8'h72; } if(col == 8) { char = 8'h79; } if(col == 9) { char = 8'h6c; } } } always_ff (clk, rst) { if_reset { frame_counter = 0; old_vsync = 0; } else { if(!vsync && old_vsync) { frame_counter = frame_counter + 1; } old_vsync = vsync; } } }

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB974242884% TRELLIS_FF143242880.6% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp39.42 MHz25 MHz $glbnet$clkt294.46 MHz250 MHz
Code

module my_code #( param WIDTH: u32 = 640, param HEIGHT: u32 = 480, param CONSOLE_COLUMNS: u32 = WIDTH / 8, param CONSOLE_ROWS: u32 = HEIGHT / 8 ) ( clk: input clock, rst: input reset, px: input u32, py: input u32, hsync: input logic, vsync: input logic, col: input u32, row: input u32, char: output u32, foreground_color: output logic<24>, background_color: output logic<24> ) { var frame_counter: u32; var old_vsync: logic; var red: logic<8>; var green: logic<8>; var blue: logic<8>; always_comb { red = (col * 4) as u8; green = py as u8; blue = frame_counter as u8; background_color = {red, green, blue}; foreground_color = 24'hff_ff_ff; char = 0; if(row == 10) { if(col == 5) { char = 8'h56; } if(col == 6) { char = 8'h65; } if(col == 7) { char = 8'h72; } if(col == 8) { char = 8'h79; } if(col == 9) { char = 8'h6c; } } } always_ff (clk, rst) { if_reset { frame_counter = 0; old_vsync = 0; } else { if(!vsync && old_vsync) { frame_counter = frame_counter + 1; } old_vsync = vsync; } } }

#FPGA #Icepi-Zero #HDL #Veryl

@[email protected] asked

module my_code #( param WIDTH: u32 = 640, param HEIGHT: u32 = 480, param CONSOLE_COLUMNS: u32 = WIDTH / 8, param CONSOLE_ROWS: u32 = HEIGHT / 8 ) ( clk: input clock, rst: input reset, px: input u32, py: input u32, hsync: input logic, vsync: input logic, col: input u32, row: input u32, char: output u32, foreground_color: output logic<24>, background_color: output logic<24> ) { var frame_counter: u32; var old_vsync: logic; var red: logic<8>; var green: logic<8>; var blue: logic<8>; always_comb { red = (col * 4) as u8; green = py as u8; blue = frame_counter as u8; background_color = {red, green, blue}; foreground_color = 24'hff_ff_ff; char = 0; if(py == 20) { if(px == 5) { char = 8'h56; } if(px == 6) { char = 8'h65; } if(px == 7) { char = 8'h72; } if(px == 8) { char = 8'h79; } if(px == 9) { char = 8'h6c; } } } always_ff (clk, rst) { if_reset { frame_counter = 0; old_vsync = 0; } else { if(!vsync && old_vsync) { frame_counter = frame_counter + 1; } old_vsync = vsync; } } }

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB909242883.7% TRELLIS_FF143242880.6% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp39.56 MHz25 MHz $glbnet$clkt279.72 MHz250 MHz
Code\n```
module my_code #(
param WIDTH: u32 = 640,
param HEIGHT: u32 = 480,
param CONSOLE_COLUMNS: u32 = WIDTH / 8,
param CONSOLE_ROWS: u32 = HEIGHT / 8
) (
clk: input clock,
rst: input reset,

px: input u32, py: input u32, hsync: input logic, vsync: input logic, col: input u32, row: input u32, char: output u32, foreground_color: output logic<24>, background_color: output logic<24>

) {
var frame_counter: u32;
var old_vsync: logic;

var red: logic<8>; var green: logic<8>; var blue: logic<8>; always_comb { red = (col * 4) as u8; green = py as u8; blue = frame_counter as u8; background_color = {red, green, blue}; foreground_color = 24'hff_ff_ff; char = 0; if(py == 20) { if(px == 5) { char = 8'h56; } if(px == 6) { char = 8'h65; } if(px == 7) { char = 8'h72; } if(px == 8) { char = 8'h79; } if(px == 9) { char = 8'h6c; } } } always_ff (clk, rst) { if_reset { frame_counter = 0; old_vsync = 0; } else { if(!vsync && old_vsync) { frame_counter = frame_counter + 1; } old_vsync = vsync; } }

}
```\n

#FPGA #Icepi-Zero #HDL #Veryl

@[email protected] asked

module my_code #( param WIDTH: u32 = 640, param HEIGHT: u32 = 480, param CONSOLE_COLUMNS: u32 = WIDTH / 8, param CONSOLE_ROWS: u32 = HEIGHT / 8 ) ( clk: input clock, rst: input reset, px: input u32, py: input u32, hsync: input logic, vsync: input logic, col: input u32, row: input u32, char: output u32, foreground_color: output logic<24>, background_color: output logic<24> ) { var frame_counter: u32; var old_vsync: logic; var red: logic<8>; var green: logic<8>; var blue: logic<8>; always_comb { red = (col * 4) as u8; green = py as u8; blue = frame_counter as u8; background_color = {red, green, blue}; foreground_color = 24'hff_ff_ff; } always_ff (clk, rst) { if_reset { frame_counter = 0; old_vsync = 0; } else { if(!vsync && old_vsync) { frame_counter = frame_counter + 1; } old_vsync = vsync; } } }

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB819242883.4% TRELLIS_FF142242880.6% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp41.6 MHz25 MHz $glbnet$clkt301.11 MHz250 MHz
Code\n\n

#FPGA #Icepi-Zero #HDL #Veryl

@[email protected] asked

module my_code #( param WIDTH: u32 = 640, param HEIGHT: u32 = 480, param CONSOLE_COLUMNS: u32 = WIDTH / 8, param CONSOLE_ROWS: u32 = HEIGHT / 8 ) ( clk: input clock, rst: input reset, px: input u32, py: input u32, hsync: input logic, vsync: input logic, col: input u32, row: input u32, char: output u32, foreground_color: output logic<24>, background_color: output logic<24> ) { var frame_counter: u32; var old_vsync: logic; // Use logic<8> to facilitate easy concatenation later var red: logic<8>; var green: logic<8>; var blue: logic<8>; always_comb { // Cast math results to 'u8' (truncation). // Veryl allows assigning u8 to logic<8>. red = (col * 4) as u8; green = py as u8; blue = frame_counter as u8; // Concatenate logic<8> elements directly background_color = {red, green, blue}; foreground_color = 24'hff_ff_ff; char = 0; } always_ff (clk, rst) { if_reset { frame_counter = 0; old_vsync = 0; } else { if !vsync && old_vsync { frame_counter = frame_counter + 1; } old_vsync = vsync; } } }

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% TRELLIS_COMB819242883.4% TRELLIS_FF142242880.6% TRELLIS_IO101975.1%
TimingClockAchievedConstraint $glbnet$clkp41.6 MHz25 MHz $glbnet$clkt301.11 MHz250 MHz
Code
module my_code #(
param WIDTH: u32 = 640,
param HEIGHT: u32 = 480,
param CONSOLE_COLUMNS: u32 = WIDTH / 8,
param CONSOLE_ROWS: u32 = HEIGHT / 8
) (
clk: input clock,
rst: input reset,

px: input u32, py: input u32, hsync: input logic, vsync: input logic, col: input u32, row: input u32, char: output u32, foreground_color: output logic<24>, background_color: output logic<24>

) {
var frame_counter: u32;
var old_vsync: logic;

// Use logic<8> to facilitate easy concatenation later var red: logic<8>; var green: logic<8>; var blue: logic<8>; always_comb { // Cast math results to 'u8' (truncation). // Veryl allows assigning u8 to logic<8>. red = (col * 4) as u8; green = py as u8; blue = frame_counter as u8; // Concatenate logic<8> elements directly background_color = {red, green, blue}; foreground_color = 24'hff_ff_ff; char = 0; } always_ff (clk, rst) { if_reset { frame_counter = 0; old_vsync = 0; } else { if !vsync && old_vsync { frame_counter = frame_counter + 1; } old_vsync = vsync; } }

}

#FPGA #Icepi-Zero #HDL #Veryl