Mastodawn

⚡ Protect your high-speed interfaces the smart way! Discover how Shanghai Leiditech’s Low Capacitance Multi-channel ±15kV ESD Protection Array delivers powerful protection without compromising signal integrity.

🚀 Read our full Part Number Selection Guide and find the perfect match for your next design!
https://medium.com/@yamy28508735/part-number-selection-guide-shanghai-leiditech-electronics-low-capacitance-multi-channel-15kv-esd-2d58f34dbd32

🔗 𝗙𝗶𝗻𝗱 𝗼𝘂𝘁 𝗺𝗼𝗿𝗲:[en.leiditech.com]
𝗖𝗼𝗻𝘁𝗮𝗰𝘁 𝘂𝘀: [email protected]

#ESDProtection #ElectronicsDesign #HighSpeedInterface #Semiconductors #SignalIntegrity #PCBDesign

🇺🇦 haxadecimal 🚫👑Jan 6

I'm trying to lay out a board with an Artix-7 FPGA (-2 speed grade), one DDR3 DRAM chip, and one SGMII PHY. I know I have to equalize the trace lengths, but assuming that all the traces are on the top layer, reasonably short but equal length, over a ground plane, is that good enough? Or do I need to worry about the trace impedances? Unfortunately I can't afford to buy Hyperlinx to do SI analysis.
#pcb #layout #fpga #ddr #signalintegrity

Versitron Dec 12

Need clean, reliable signal distribution for pro-grade video?

Versitron delivers rugged solutions including audio-visual equipment SDI amplifiers and EMI-shielded video amplifiers designed for stable, noise-free performance in demanding environments.

#Versitron #VideoAmplifier #SDI #AVTech #FiberOptics #SignalIntegrity #ProAV

Doreen Xu Dec 11

Looking for a domestic alternative to PESD1V2Y1BSF, ESDL2012MX4T5G, RClamp1011ZC, or PS1201-D32?
Meet Leiditech’s ULC0121CLV — ultra-low capacitance, ultra-low clamp voltage, and built for next-gen high-speed protection.
Smaller, faster, safer. Contact us .😊

🔗 𝗙𝗶𝗻𝗱 𝗼𝘂𝘁 𝗺𝗼𝗿𝗲:[en.leiditech.com]
𝗖𝗼𝗻𝘁𝗮𝗰𝘁 𝘂𝘀: [email protected]

https://medium.com/@yamy28508735/pesd1v2y1bsf-esdl2012mx4t5g-etc-are-domestic-alternatives-to-ulc0121clv-ca9f0051d4cc

#ESDProtection #TVSdiode #ULC0121CLV #ElectronicsDesign #HardwareEngineering #Leiditech #Components #signalintegrity

MosChip®Nov 20

Avoid PCB-level resistance by simulating the design for a fail-safe, high-performance hardware.
Watch the full webinar to learn how to optimize and unify hardware design for next-gen products: https://zurl.co/lmdnH
#pcbdesign #powerintegrity #signalintegrity

Mathias Magdowski Aug 24, 2025

Ich freue mich über das "Certificate of Appreciation" for "outstanding contributions to the administration and overall success of the IEEE EMC Society as a #DistinguishedLecturer (2023-2024)", die ich neben Bob Johnk, Yarú Méndez und Jianqing Wang auf dem IEEE International Symposium on #ElectromagneticCompatibility, #SignalIntegrity and #PowerIntegrity #IEEE_ESP25 in Raleigh, NC, USA bekommen habe.

Vielen Dank an Andreas Hardock vom German #EMC Chapter für das Foto!

rawe Jan 17, 2024

Todays #electronicsengineering #educational #video tip: #youtube channel FesZ #Electronics (currently 45600 subscribers): https://www.youtube.com/channel/UCsWRAAMs_Cn78_kRLSpkb6w

The videos feature topics like #emc, #ham, #radio, #smps, #pll, #rf, #signalintegrity, #audio, #analogelectronics

FesZ Electronics

A project about projects. FesZ Electronics is a channel about various electronic projects I spend my free time doing. It will go from educational stuff like tutorials, to teardown reviews to just putting ideas into practice. The point is to do something with educational value, not just fun. Have a look, leave a comment and come back again if you like what you've found! If you wish to support my activities you can have a look at my patreon page: https://www.patreon.com/feszelectronics

YouTube

Show thread

flpvsk Jan 8, 2024

Watching this talk little bits at a time

not because it's hard to digest (in fact the delivery is superb)

but because I'm getting flashbacks of the boards I designed recently and it hurts 🥲

#pcb #pcbdesign #emi #signalintegrity

Graham Sutherland / Polynomial Jul 26, 2023

faffed about with some more simulation for transmission line termination on @mos_8502's ZSA bus. Iooks like serial termination on the cards and VTT termination on the backplane is probably workable, but in case someone has a better idea I asked about it on StackExchange.

if you're reading this and you've designed stuff with 50MHz+ single-ended signals that required termination, your thoughts would be much appreciated.

#Electronics #SignalIntegrity

https://electronics.stackexchange.com/questions/675402/drive-strength-and-termination-on-a-50mhz-multi-card-backplane-bus

Drive strength and termination on a 50MHz multi-card backplane bus

I'm helping someone design a spec for a computing ecosystem based on Z80 and Eurocard. One of the challenges is that we want to support modern Z80 chips clocked at up to 50MHz, which means we have ...

Electrical Engineering Stack Exchange