51b30vFeb 24

Presented my experiences using #cocotb professionaly at FPGA Forum in Trondheim two weeks ago.

https://www.linkedin.com/posts/eidsvoll-electronics-as_eidel-at-fpga-forum-2026-eidel-engelsk-activity-7432046803782438912-76yk?utm_source=social_share_send&utm_medium=android_app&rcm=ACoAACZpHL8B95Cn3a9XFUW06rkzrFc7CgvHSps&utm_campaign=copy_link

EIDEL at FPGA Forum 2026 - Eidel - Engelsk | EIDEL AS

EIDEL AS had the pleasure of contributing with two presentations at FPGA Forum 2026 in Trondheim this year. Sindre Bergsvik Øvstegård shared experiences from using Cocotb as the main verification framework in real projects— focusing on practical takeaways, useful features, and what implications a shift to Python‑based verification did for our workflows. Sylvain Tertois presented the development of space solutions based entirely on FPGA. By relying solely on modular FPGA logic, we’ve been able to achieve high reliability, strong testability, and efficient use of FPGA resources-an approach well‑suited for mission critical applications. Great discussions, great community, and always a highlight to meet fellow FPGA developers and engineers in Trondheim. Looking forward to next year! https://lnkd.in/eyDMTZBv

FLFOct 21

Cocotb version 2.0

https://linuxfr.org/news/sortie-de-cocotb-version-2-0-0

#Cocotb #fpga #python #vhdl #verilog #systemverilog

Sortie de Cocotb version 2.0.0 - LinuxFr.org

L’actualité du logiciel libre et des sujets voisins (DIY, Open Hardware, Open Data, les Communs, etc.), sur un site francophone contributif géré par une équipe bénévole par et pour des libristes enthousiastes

Show threadCayetano SantosOct 10

@guix Other than as package manager on top of #archlinux, I’m using #guix for electronics design, mostly #vhdl and #fpga related stuff.

I run simulations with help of #hdlmake using #ghdl compiler, #osvvm for verification, #cocotb for testbenches, #yosys for synthesis, #nextpnr for placement and routing and #openFPGALoader for flashing. Finally, I use my own Guix channel to package gateware and run #ci tests on #sourcehut Guix image. A demo toy example of this runs here

https://builds.sr.ht/~csantosb/job/1585413

FLFSep 16, 2025

Cocotb v2.0.0 \o/

https://github.com/cocotb/cocotb/releases/tag/v2.0.0

#cocotb #flf #release #python #verilog #vhdl #icarus #ghdl #nvc #verilator

Release 2.0.0 · cocotb/cocotb

Release notes: https://docs.cocotb.org/en/v2.0.0/release_notes.html PyPI release: https://pypi.org/project/cocotb/2.0.0

GitHub
Show threadFluxAug 19, 2025

Isle Verilog modules include #cocotb tests and reference docs. Writing docs is time consuming but worthwhile. It's hard to learn from existing designs without them. #FPGA

Here's a simple example; it could be better, but it's something to build on: https://github.com/projf/isle/blob/main/hardware/gfx/doc/display.md

FLFJul 17, 2025

Cocotb cherche des béta testeurs pour sa version 2.0 \o/

#python #cocotb #test #fpga #flf

poleguy looking for lost toolsMay 14, 2025

The search engines are failing me.

Dear Lazy Web:
If I wanted to enumerate the hierarchy of a design at the beginning of a cocotb test bench, how would I do it? (I'm aware of _discover_all(), but can't figure out how to iterate the results to print them.)

Extra credit: How do I get an interactive debugger to break within the cocotb python code if I call cocotb from pytest? It seems to run the pytest code in the debugger, but not the cocotb code.

#fpga #cocotb #lazyweb #python #vhdl #verilog

Cayetano SantosMar 6, 2025

#cocotb, a #freesoftware cosimulation testbench environment for verifying #VHDL and #SystemVerilog #RTL using #Python, is part now of #guixscience channel. It may be used as any other #guix package with a simple

guix install python-cocotb

This means too that pre-built substitutes are available online 🥳.

#modernhw

Show threadpoleguy looking for lost toolsApr 22, 2024
@Tathar I would like to see a good one too. I'm all my years doing #vhdl and #verilog for a living the best test benches I ever have seen have just read in golden vectors and wrote out result vectors so they could be checked by an external script. We now use #cocotb and I'm starting to like it. I don't feel an hdl is a good match for testbench work. Maybe for a fixture layer connecting hdl blocks. But testbenches are not hardware. Why would we expect an hdl would do well for it?
Jakub Cabal [OLD]Mar 21, 2024
Implementing HDL verification using #UVM is annoying and tedious. So #cocotb seems to be the right choice. #FPGA #Python #systemverilog #VHDL