poleguy looking for lost toolsMaking it match the sim.
Clock shows one clock between last data transition and rising edge of we_n, scope shows two.
Getting closer!
philtor 🇺🇦🌻This week experimented with adding a matmul & sorting accelerators (and opcodes for both) to PicoRV32 using the PCPI interface. Also added support for those ops to the Spike RISCV simulator. Yes, Claude helped a huge amount with these tasks which would've likely taken weeks otherwise. The design simulates (Verilator) & sythesizes (yosys) and I can generate a bitstream for both GateMateA1 and ECP5 (OrangeCrab board)
Wojtek PowiertowskiPOSSE is done. Work is peaking. But I have a Xilinx VC707 and a pre-production Skylake-X box collecting dust, and an FPGA side project taking shape in my head (399 words)
#fpga #verilator #hardwaredev #sideproject #posse
uvok cheetahMy Nandgame CPU now has an Assembler.
Yes, it's LLM generated.
I run into the problem that I want to solve problem X, for for that, I need to solve Y, Z, Q, a.s.o first.
I needed a shortcut.
Anyway, I now can sum the numbers from 0 to 10.
I need to manually calculate jump positions. No labels.
I have no proper halt instruction and will probably simply use the nand2tetris convention of "these instruction bits need to be 1". Which is fugly for future extensions.
I have no idea how to properly solve this.
https://git.uvok.de/fpga-exper/tree/nandgame/assembler?h=main
More makefile rules.
Trying to get #verilator to work
It turns out I already had the verilator lint support installed in my #vscode
https://github.com/Migilint/vscode-verilog-linter
And once I compiled/installed #verilator (and set up the path, which unfortunately seems to be manual), it is integrated nicely. It doesn't seem to run automatically though as I type.
FLF
DustinI'm playing with open source simulators again. Verilator and GTKWave still seem to be the masters of the space. I used to use IcarusVerilog for simulating, but Verilator is much faster.
Analog values on a bus are always good visuals for debugging things. I learned to use this mode when trying to visually qualify k characters on a serial link.
This screenshot is the output of an LFSR block with a 16bit polynomial resulting in a 64k value space.
@thezoq2 Begin page 392 in pdf.
#fpga #surfer #verilog #vhdl #spinalHDL #chisel #icarus #verilator #simulation #opensource #gtkwave #waveform
HabrНабрасываем на Verilator
Эта статья не является прямым продолжение статьи Время собирать пакеты , но затрагивает связанные темы. Учимся создавать артефакты в рамках концепции Инфраструктура как Артефакт. Будем разворачивать Verilator в Kubernetes.
