HabrНабрасываем на Verilator
Эта статья не является прямым продолжение статьи Время собирать пакеты , но затрагивает связанные темы. Учимся создавать артефакты в рамках концепции Инфраструктура как Артефакт. Будем разворачивать Verilator в Kubernetes.
Из студентов в инженеры: как перестать бояться и полюбить системную верификацию
Привет, Хабр! На связи Михаил Степанов, инженер в группе функциональной верификации YADRO. Еще в прошлом году мы с моим коллегой Романом Казаченко участвовали в хакатоне по разработке микропроцессоров как студенты, а сейчас — помогаем с задачами для SoC Design Challenge как сотрудники компании-организатора. В статье расскажем, что ждет участников трека «Системная верификация СнК» в этом году и как подготовиться к этому испытанию. Если вы не планируете участвовать в хакатоне, но вам интересно, как инженеры тестируют системы на кристалле перед запуском в производство, эта статья тоже будет вам полезна. На примере заданий хакатона я кратко объясню, что такое системная верификация, из каких блоков состоят СнК и какие инструменты используются для их тестирования.
https://habr.com/ru/companies/yadro/articles/885854/
#SoC_design #функциональная_верификация #системная_верификация #QEMU #verilog #verilator #система_на_кристалле #хакатон #SoC_Design_Challenge
Max KorbelExciting update for the ROHD community! We're pleased to announce the release of ROHD Cosim v0.3.0, now supporting in/out ports and Verilator for enhanced simulation. Also, ROHD v0.6.2 is out, featuring some bug fixes and improved adder syntax in SystemVerilog. https://buff.ly/3WLth4y #rohd #opensource #hardware #hdl #cosim #verilator
TheZoq2🎉 Spade v0.8.0 has been released 🎉
This release extends the standard library, fixes a whole bunch of small pitfalls, and includes several improvements around tests!
The std-lib now has a higher level wrapper around #fpga block-rams, primitives for clock domain crossing, and reduce_* functions added by @0xC01DC0FFEE
Finally, improved #Verilator support allows cool stuff in tests. The video shows this being used to visualize memory accesses in my camera project
Kenneth OUpgraded #verilator from 5.018 to 5.020 in #MacPorts. Just waiting for the CI and merge now.
Fediverse DirectoryI think that it is very hard to debug complex #verilog circuits. So many things happening at the same time. So I am about to start writing C++ consistency checks for the #Verilator simulator. If this signal is this way, then that signal should be that way. Run a test, if it fails, guess at the bug, write a consistency test, and run it again.
Very different from testing each block, sadly the #J1 CPU + #Forth is one complex circuit.
#Mecrisp
Andrewbasically there has to be an AMS HDL (hardware definition language for analog and mixed signals, mixed with digital) for which there is a type-system, a calculus, a logic for it
not really sure what it should be, maybe a variant of π-calculus, IDK
whatever, people can only make hardware if there are tools for it; there have to be FLOSS CADs for FLOSS h/w, otherwise it just doesn't make sense, relying on a proprietary stuff just to even simulate it — #Verilator is very important in this regard, though ATM I'm not even sure it simulates correctly
and for analog there of course are Octave and Scipy/Numpy, but I can't tell how good these are for RF and transceivers; QUCS is nice too but again I can't tell how mature it is — is it only good for teaching or
not really sure what it should be, maybe a variant of π-calculus, IDK
whatever, people can only make hardware if there are tools for it; there have to be FLOSS CADs for FLOSS h/w, otherwise it just doesn't make sense, relying on a proprietary stuff just to even simulate it — #Verilator is very important in this regard, though ATM I'm not even sure it simulates correctly
and for analog there of course are Octave and Scipy/Numpy, but I can't tell how good these are for RF and transceivers; QUCS is nice too but again I can't tell how mature it is — is it only good for teaching or
I've been doing functional verification (behavioral modeling) for a while now, and it still is kinda difficult to explain, even to myself, how the synthesisable (DUT/RTL) and non-synthesisable (TB) code interact
I wouldn't be able to write my own simulator now (similar to #Verilator)
I wouldn't be able to write my own simulator now (similar to #Verilator)
Didier Malenfant 
If you’re using @panic ’s Nova to edit your Verilog files, you'll be happy to know that @tsalvo ‘s Verilog extension now supports linting too via verilator…
nova://extension/?id=com.tomsalvo.verilog&name=Verilog
