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module my_code #(
parameter int WIDTH = 640,
parameter int HEIGHT = 480,
parameter int CONSOLE_COLUMNS = WIDTH / 8,
parameter int CONSOLE_ROWS = HEIGHT / 8
)(
input logic clk,
input logic rst,
input int px,
input int py,
input logic hsync,
input logic vsync,
input int col,
input int row,
output int char,
output logic [23:0] foreground_color,
output logic [23:0] background_color,
output logic [7:0] uart_data,
input logic uart_ready,
output logic uart_valid
);
// -------------------------------------------------------------
// Animated XOR-plasma background + pulsing banner + UART beacon
// -------------------------------------------------------------
logic [31:0] frame_counter = '0;
logic old_vsync = '0;
// ---- Plasma color computation -------------------------------
logic [7:0] t;
logic [7:0] r, g, b;
logic [7:0] px8, py8;
logic [7:0] dx, dy, dist;
assign t = frame_counter[7:0];
assign px8 = px[7:0];
assign py8 = py[7:0];
// crude radial distance from a moving center
assign dx = px8 - t;
assign dy = py8 + t;
assign dist = dx ^ dy;
assign r = dist + t;
assign g = (px8 ^ py8) + (t << 1);
assign b = (px8 + py8) - t;
// ---- Banner overlay -----------------------------------------
// Console grid: 80 cols x 60 rows. Banner: row 28, "** PLASMA DEMO **"
// 17 chars centered -> start col = (80-17)/2 = 31
int rel_b;
int rel_f;
int hex_nib;
logic [7:0] hex_char;
assign rel_b = col - 31;
assign rel_f = col - 34;
// pick the hex nibble corresponding to rel_f position 5..12
always_comb begin
case (rel_f)
5: hex_nib = frame_counter[31:28];
6: hex_nib = frame_counter[27:24];
7: hex_nib = frame_counter[23:20];
8: hex_nib = frame_counter[19:16];
9: hex_nib = frame_counter[15:12];
10: hex_nib = frame_counter[11:8];
11: hex_nib = frame_counter[7:4];
12: hex_nib = frame_counter[3:0];
default: hex_nib = 8'h0;
endcase
if (hex_nib < 8'd10)
hex_char = 8'h30 + hex_nib; // '0'..'9'
else
hex_char = 8'h41 + (hex_nib - 8'd10); // 'A'..'F'
end
always_comb begin
background_color = {r, g, b};
foreground_color = 24'hFFFFFF;
char = 0;
// ---- Title banner on row 28 -----------------------------
if (row == 28) begin
case (rel_b)
0: char = "*";
1: char = "*";
2: char = " ";
3: char = "P";
4: char = "L";
5: char = "A";
6: char = "S";
7: char = "M";
8: char = "A";
9: char = " ";
10: char = "D";
11: char = "E";
12: char = "M";
13: char = "O";
14: char = " ";
15: char = "*";
16: char = "*";
default: char = 0;
endcase
if (rel_b >= 0 && rel_b < 17)
foreground_color = {t, 8'hFF, ~t};
end
// ---- Frame counter line on row 30 -----------------------
if (row == 30) begin
case (rel_f)
0: char = "F";
1: char = "R";
2: char = "M";
3: char = ":";
4: char = " ";
5: char = hex_char;
6: char = hex_char;
7: char = hex_char;
8: char = hex_char;
9: char = hex_char;
10: char = hex_char;
11: char = hex_char;
12: char = hex_char;
default: char = 0;
endcase
if (rel_f >= 0 && rel_f <= 12)
foreground_color = 24'h00FF66;
end
// ---- Footer "YOSYS + SV = LOVE" on row 56 ---------------
if (row == 56) begin
case (col - 32)
0: char = "Y";
1: char = "O";
2: char = "S";
3: char = "Y";
4: char = "S";
5: char = " ";
6: char = "+";
7: char = " ";
8: char = "S";
9: char = "V";
10: char = " ";
11: char = "=";
12: char = " ";
13: char = "L";
14: char = "O";
15: char = "V";
16: char = "E";
default: char = 0;
endcase
if ((col - 32) >= 0 && (col - 32) < 17)
foreground_color = {8'hFF, t, t};
end
end
// -------------------------------------------------------------
// UART beacon: send "** FPGA PLASMA DEMO ** Frame=XXXXXXXX\r\n"
// -------------------------------------------------------------
// 42 bytes total
localparam int MSG_LEN = 42;
logic [5:0] msg_idx = '0;
logic sending = 1'b0;
logic [23:0] throttle = '0;
logic [31:0] sent_frame = '0;
logic [7:0] msg_byte;
logic [3:0] nib;
always_comb begin
nib = 4'h0;
case (msg_idx)
6'd0: msg_byte = "*";
6'd1: msg_byte = "*";
6'd2: msg_byte = " ";
6'd3: msg_byte = "F";
6'd4: msg_byte = "P";
6'd5: msg_byte = "G";
6'd6: msg_byte = "A";
6'd7: msg_byte = " ";
6'd8: msg_byte = "P";
6'd9: msg_byte = "L";
6'd10: msg_byte = "A";
6'd11: msg_byte = "S";
6'd12: msg_byte = "M";
6'd13: msg_byte = "A";
6'd14: msg_byte = " ";
6'd15: msg_byte = "D";
6'd16: msg_byte = "E";
6'd17: msg_byte = "M";
6'd18: msg_byte = "O";
6'd19: msg_byte = " ";
6'd20: msg_byte = "*";
6'd21: msg_byte = "*";
6'd22: msg_byte = " ";
6'd23: msg_byte = "F";
6'd24: msg_byte = "r";
6'd25: msg_byte = "a";
6'd26: msg_byte = "m";
6'd27: msg_byte = "e";
6'd28: msg_byte = "=";
6'd29: begin msg_byte = 8'h00; nib = sent_frame[31:28]; end
6'd30: begin msg_byte = 8'h00; nib = sent_frame[27:24]; end
6'd31: begin msg_byte = 8'h00; nib = sent_frame[23:20]; end
6'd32: begin msg_byte = 8'h00; nib = sent_frame[19:16]; end
6'd33: begin msg_byte = 8'h00; nib = sent_frame[15:12]; end
6'd34: begin msg_byte = 8'h00; nib = sent_frame[11:8]; end
6'd35: begin msg_byte = 8'h00; nib = sent_frame[7:4]; end
6'd36: begin msg_byte = 8'h00; nib = sent_frame[3:0]; end
6'd37: msg_byte = "!";
6'd38: msg_byte = "\r";
6'd39: msg_byte = "\n";
default: msg_byte = 8'h00;
endcase
if (msg_idx >= 6'd29 && msg_idx <= 6'd36) begin
if (nib < 4'd10)
msg_byte = 8'h30 + {4'b0, nib};
else
msg_byte = 8'h41 + {4'b0, nib} - 8'd10;
end
uart_data = msg_byte;
uart_valid = sending && (msg_idx < MSG_LEN[5:0]);
end
always_ff @(posedge clk) begin
if (vsync == 1'b0 && old_vsync == 1'b1) begin
frame_counter <= frame_counter + 1;
end
old_vsync <= vsync;
if (sending) begin
if (uart_ready && uart_valid) begin
if (msg_idx == MSG_LEN[5:0] - 1) begin
sending <= 1'b0;
msg_idx <= '0;
end else begin
msg_idx <= msg_idx + 1;
end
end
end else begin
throttle <= throttle + 1;
if (throttle[22] == 1'b1) begin
sending <= 1'b1;
throttle <= '0;
sent_frame <= frame_counter;
end
end
end
endmodule
Success!
UART Output
** FPGA PLASMA DEMO ** Frame=00000131!
\0\0** FPGA PLASMA DEMO ** Frame=0000013C!
\0\0** FPGA PLASMA DEMO ** Frame=00000146!
\0\0** FPGA PLASMA DEMO ** Frame=00000150!
\0\0** FPGA PLASMA DEMO ** Frame=0000015A!
\0\0** FPGA PLASMA DEMO ** Frame=00000164!
\0\0** FPGA PLASMA DEMO ** Frame=0000016F!
\0\0** FPGA PLASMA DEMO ** Frame=00000179!
\0\0** FPGA PLASMA DEMO ** Frame=00000183!
\0\0** FPGA PLASMA DEMO ** Frame=0000018D!
\0\0** FPGA PLASMA DEMO ** Frame=00000197!
\0\0** FPGA PLASMA DEMO ** Frame=000001A2!
\0\0** FPGA PLASMA DEMO ** Frame=000001AC!
\0\0** FPGA PLASMA DEMO ** Frame=000001B6!
\0\0** FPGA PLASMA DEMO ** Frame=000001C0!
\0\0** FPGA PLASMA DEMO ** Frame=000001CA!
\0\0** FPGA PLASMA DEMO ** Frame=000001D5!
\0\0** FPGA PLASMA DEMO ** Frame=000001DF!
\0\0** FPGA PLASMA DEMO ** Frame=000001E9!
\0\0** FPGA PLASMA DEMO ** Frame=000001F3!
\0\0** FPGA PLASMA DEMO ** Frame=000001FD!
\0\0** FPGA PLASMA DEMO ** Frame=00000208!
\0\0** FPGA PLASMA DEMO ** Frame=00000212!
\0\0** FPGA PLASMA DEMO ** Frame=0000021C!
\0\0** FPGA PLASMA DEMO ** Frame=00000226!
\0\0** FPGA PLASMA DEMO ** Frame=00000230!
\0\0** FPGA PLASMA DEMO ** Frame=0000023B!
\0\0** FPGA PLASMA DEMO ** Frame=00000245!
\0\0** FPGA PLASMA DEMO ** Frame=0000024F!
\0\0** FPGA PLASMA DEMO ** Frame=00000259!
\0\0** FPGA PLASMA DEMO ** Frame=00000263!
\0\0** FPGA PLASMA DEMO ** Frame=0000026E!
\0\0** FPGA PLASMA DEMO ** Frame=00000278!
\0\0** FPGA PLASMA DEMO ** Frame=00000282!
\0\0** FPGA PLASMA DEMO ** Frame=0000028C!
\0\0** FPGA PLASMA DEMO ** Frame=00000296!
\0\0** FPGA PLASMA DEMO ** Frame=000002A1!
\0\0** FPGA PLASMA DEMO ** Frame=000002AB!
\0\0** FPGA PLASMA DEMO ** Frame=000002B5!
\0\0** FPGA PLASMA DEMO ** Frame=000002BF!
\0\0** FPGA PLASMA DEMO ** Frame=000002C9!
\0\0** FPGA PLASMA DEMO ** Frame=000002D4!
\0\0** FPGA PLASMA DEMO ** Frame=000002DE!
\0\0** FPGA PLASMA DEMO ** Frame=000002E8!
\0\0** FPGA PLASMA DEMO ** Frame=000002F2!
\0\0** FPGA PLASMA DEMO ** Frame=000002FC!
\0\0** FPGA PLASMA DEMO ** Frame=00000307!
\0\0** FPGA PLASMA DEMO ** Frame=00000311!
\0\0** FPGA PLASMA DEMO ** Frame=0000031B!
\0\0** FPGA PLASMA DEMO ** Frame=00000325!
\0\0** FPGA PLASMA DEMO ** Frame=0000032F!
\0\0** FPGA PLASMA DEMO ** Frame=00000339!
\0\0** FPGA PLASMA DEMO ** Frame=00000344!
\0\0** FPGA PLASMA DEMO ** Frame=0000034E!
\0\0** FPGA PLASMA DEMO ** Frame=00000358!
\0\0** FPGA PLASMA DEMO ** Frame=00000362!
\0\0** FPGA PLASMA DEMO ** Frame=0000036C!
\0\0** FPGA PLASMA DEMO ** Frame=00000377!
\0\0** FPGA PLASMA DEMO ** Frame=00000381!
\0\0** FPGA PLASMA DEMO ** Frame=0000038B!
\0\0** FPGA PLASMA DEMO ** Frame=00000395!
\0\0** FPGA PLASMA DEMO ** Frame=0000039F!
\0\0** FPGA PLASMA DEMO ** Frame=000003AA!
\0\0** FPGA PLASMA DEMO ** Frame=000003B4!
\0\0** FPGA PLASMA DEMO ** Frame=000003BE!
\0\0** FPGA PLASMA DEMO ** Frame=000003C8!
\0\0** FPGA PLASMA DEMO ** Frame=000003D2!
\0\0** FPGA PLASMA DEMO ** Frame=000003DD!
\0\0** FPGA PLASMA DEMO ** Frame=000003E7!
\0\0** FPGA PLASMA DEMO ** Frame=000003F1!
\0\0** FPGA PLASMA DEMO ** Frame=000003FB!
\0\0** FPGA PLASMA DEMO ** Frame=00000405!
\0\0** FPGA PLASMA DEMO ** Frame=00000410!
\0\0** FPGA PLASMA DEMO ** Frame=0000041A!
\0\0** FPGA PLASMA DEMO ** Frame=00000424!
\0\0** FPGA PLASMA DEMO ** Frame=0000042E!
\0\0** FPGA PLASMA DEMO ** Frame=00000438!
\0\0** FPGA PLASMA DEMO ** Frame=00000443!
\0\0** FPGA PLASMA DEMO ** Frame=0000044D!
\0\0** FPGA PLASMA DEMO ** Frame=00000457!
\0\0** FPGA PLASMA DEMO ** Frame=00000461!
\0\0** FPGA PLASMA DEMO ** Frame=0000046B!
\0\0** FPGA PLASMA DEMO ** Frame=00000476!
\0\0** FPGA PLASMA DEMO ** Frame=00000480!
\0\0** FPGA PLASMA DEMO ** Frame=0000048A!
\0\0** FPGA PLASMA DEMO ** Frame=00000494!
\0\0** FPGA PLASMA DEMO ** Frame=0000049E!
\0\0** FPGA PLASMA DEMO ** Frame=000004A9!
\0\0** FPGA PLASMA DEMO ** Frame=000004B3!
\0\0** FPGA PLASMA DEMO ** Frame=000004BD!
\0\0** FPGA PLASMA DEMO ** Frame=000004C7!
\0\0** FPGA PLASMA DEMO ** Frame=000004D1!
\0\0** FPGA PLASMA DEMO ** Frame=000004DC!
\0\0** FPGA PLASMA DEMO ** Frame=000004E6!
\0\0** FPGA PLASMA DEMO ** Frame=000004F0!
\0\0** FPGA PLASMA DEMO ** Frame=000004FA!
\0\0** FPGA PLASMA DEMO ** Frame=00000504!
\0\0** FPGA PLASMA DEMO ** Frame=0000050F!
\0\0** FPGA PLASMA DEMO ** Frame=00000519!
\0\0** FPGA PLASMA DEMO ** Frame=00000523!
\0\0** FPGA PLASMA DEMO ** Frame=0000052D!
\0\0** FPGA PLASMA DEMO ** Frame=00000537!
\0\0** FPGA PLASMA DEMO ** Frame=00000542!
\0\0** FPGA PLASMA DEMO ** Frame=0000054C!
\0\0** FPGA PLASMA DEMO ** Frame=00000556!
\0\0** FPGA PLASMA DEMO ** Frame=00000560!
\0\0** FPGA PLASMA DEMO ** Frame=0000056A!
\0\0** FPGA PLASMA DEMO ** Frame=00000575!
\0\0** FPGA PLASMA DEMO ** Frame=0000057F!
\0\0** FPGA PLASMA DEMO ** Frame=00000589!
\0\0** FPGA PLASMA DEMO ** Frame=00000593!
\0\0** FPGA PLASMA DEMO ** Frame=0000059D!
\0\0** FPGA PLASMA DEMO ** Frame=000005A8!
\0\0** FPGA PLASMA DEMO ** Frame=000005B2!
\0\0** FPGA PLASMA DEMO ** Frame=000005BC!
\0\0** FPGA PLASMA DEMO ** Frame=000005C6!
\0\0** FPGA PLASMA DEMO ** Frame=000005D0!
\0\0** FPGA PLASMA DEMO ** Frame=000005DB!
\0\0** FPGA PLASMA DEMO ** Frame=000005E5!
\0\0** FPGA PLASMA DEMO ** Frame=000005EF!
\0\0** FPGA PLASMA DEMO ** Frame=000005F9!
\0\0** FPGA PLASMA DEMO ** Frame=00000603!
\0\0** FPGA PLASMA DEMO ** Frame=0000060E!
\0\0** FPGA PLASMA DEMO ** Frame=00000618!
\0\0** FPGA PLASMA DEMO ** Frame=00000622!
\0\0** FPGA PLASMA DEMO ** Frame=0000062C!
\0\0** FPGA PLASMA DEMO ** Frame=00000636!
\0\0** FPGA PLASMA DEMO ** Frame=00000641!
\0\0** FPGA PLASMA DEMO ** Frame=0000064B!
\0\0** FPGA PLASMA DEMO ** Frame=00000655!
\0\0** FPGA PLASMA DEMO ** Frame=0000065F!
\0\0** FPGA PLASMA DEMO ** Frame=00000669!
\0\0** FPGA PLASMA DEMO ** Frame=00000674!
\0\0** FPGA PLASMA DEMO ** Frame=0000067E!
\0\0** FPGA PLASMA DEMO ** Frame=00000688!
\0\0** FPGA PLASMA DEMO ** Frame=00000692!
\0\0** FPGA PLASMA DEMO ** Frame=0000069C!
\0\0** FPGA PLASMA DEMO ** Frame=000006A7!
\0\0** FPGA PLASMA DEMO ** Frame=000006B1!
\0\0** FPGA PLASMA DEMO ** Frame=000006BB!
\0\0** FPGA PLASMA DEMO ** Frame=000006C5!
\0\0** FPGA PLASMA DEMO ** Frame=000006CF!
\0\0** FPGA PLASMA DEMO ** Frame=000006DA!
\0\0** FPGA PLASMA DEMO ** Frame=000006E4!
\0\0** FPGA PLASMA DEMO ** Frame=000006EE!
\0\0** FPGA PLASMA DEMO ** Frame=000006F8!
\0\0** FPGA PLASMA DEMO ** Frame=00000702!
\0\0** FPGA PLASMA DEMO ** Frame=0000070D!
\0\0** FPGA PLASMA DEMO ** Frame=00000717!
\0\0** FPGA PLASMA DEMO ** Frame=00000721!
\0\0** FPGA PLASMA DEMO ** Frame=0000072B!
\0\0** FPGA PLASMA DEMO ** Frame=00000735!
\0\0** FPGA PLASMA DEMO ** Frame=00000740!
\0\0** FPGA PLASMA DEMO ** Frame=0000074A!
\0\0** FPGA PLASMA DEMO ** Frame=00000754!
\0\0** FPGA PLASMA DEMO ** Frame=0000075E!
\0\0** FPGA PLASMA DEMO ** Frame=00000768!
\0\0** FPGA PLASMA DEMO ** Frame=00000773!
\0\0** FPGA PLASMA DEMO ** Frame=0000077D!
\0\0** FPGA PLASMA DEMO ** Frame=00000787!
\0\0** FPGA PLASMA DEMO ** Frame=00000791!
\0\0** FPGA PLASMA DEMO ** Frame=0000079B!
\0\0** FPGA PLASMA DEMO ** Frame=000007A6!
\0\0** FPGA PLASMA DEMO ** Frame=000007B0!
\0\0** FPGA PLASMA DEMO ** Frame=000007BA!
\0\0** FPGA PLASMA DEMO ** Frame=000007C4!
\0\0** FPGA PLASMA DEMO ** Frame=000007CE!
\0\0** FPGA PLASMA DEMO ** Frame=000007D9!
\0\0** FPGA PLASMA DEMO ** Frame=000007E3!
\0\0** FPGA PLASMA DEMO ** Frame=000007ED!
\0\0** FPGA PLASMA DEMO ** Frame=000007F7!
\0\0** FPGA PLASMA DEMO ** Frame=00000801!
\0\0** FPGA PLASMA DEMO ** Frame=0000080C!
\0\0** FPGA PLASMA DEMO ** Frame=00000816!
\0\0** FPGA PLASMA DEMO ** Frame=00000820!
\0\0
UtilizationCellUsedAvailableUsage
DCCA2563.6%
EHXPLLL1250.0%
TRELLIS_COMB1699242887.0%
TRELLIS_FF253242881.0%
TRELLIS_IO111975.6%
TimingClockAchievedConstraint
$glbnet$clkp39.66 MHz25 MHz
$glbnet$clkt320.41 MHz250 MHz
Code
module my_code #(
parameter int WIDTH = 640,
parameter int HEIGHT = 480,
parameter int CONSOLE_COLUMNS = WIDTH / 8,
parameter int CONSOLE_ROWS = HEIGHT / 8
)(
input logic clk,
input logic rst,
input int px,
input int py,
input logic hsync,
input logic vsync,
input int col,
input int row,
output int char,
output logic [23:0] foreground_color,
output logic [23:0] background_color,
output logic [7:0] uart_data,
input logic uart_ready,
output logic uart_valid
);
// -------------------------------------------------------------
// Animated XOR-plasma background + pulsing banner + UART beacon
// -------------------------------------------------------------
logic [31:0] frame_counter = '0;
logic old_vsync = '0;
// ---- Plasma color computation -------------------------------
logic [7:0] t;
logic [7:0] r, g, b;
logic [7:0] px8, py8;
logic [7:0] dx, dy, dist;
assign t = frame_counter[7:0];
assign px8 = px[7:0];
assign py8 = py[7:0];
// crude radial distance from a moving center
assign dx = px8 - t;
assign dy = py8 + t;
assign dist = dx ^ dy;
assign r = dist + t;
assign g = (px8 ^ py8) + (t << 1);
assign b = (px8 + py8) - t;
// ---- Banner overlay -----------------------------------------
// Console grid: 80 cols x 60 rows. Banner: row 28, "** PLASMA DEMO **"
// 17 chars centered -> start col = (80-17)/2 = 31
int rel_b;
int rel_f;
int hex_nib;
logic [7:0] hex_char;
assign rel_b = col - 31;
assign rel_f = col - 34;
// pick the hex nibble corresponding to rel_f position 5..12
always_comb begin
case (rel_f)
5: hex_nib = frame_counter[31:28];
6: hex_nib = frame_counter[27:24];
7: hex_nib = frame_counter[23:20];
8: hex_nib = frame_counter[19:16];
9: hex_nib = frame_counter[15:12];
10: hex_nib = frame_counter[11:8];
11: hex_nib = frame_counter[7:4];
12: hex_nib = frame_counter[3:0];
default: hex_nib = 8'h0;
endcase
if (hex_nib < 8'd10)
hex_char = 8'h30 + hex_nib; // '0'..'9'
else
hex_char = 8'h41 + (hex_nib - 8'd10); // 'A'..'F'
end
always_comb begin
background_color = {r, g, b};
foreground_color = 24'hFFFFFF;
char = 0;
// ---- Title banner on row 28 -----------------------------
if (row == 28) begin
case (rel_b)
0: char = "*";
1: char = "*";
2: char = " ";
3: char = "P";
4: char = "L";
5: char = "A";
6: char = "S";
7: char = "M";
8: char = "A";
9: char = " ";
10: char = "D";
11: char = "E";
12: char = "M";
13: char = "O";
14: char = " ";
15: char = "*";
16: char = "*";
default: char = 0;
endcase
if (rel_b >= 0 && rel_b < 17)
foreground_color = {t, 8'hFF, ~t};
end
// ---- Frame counter line on row 30 -----------------------
if (row == 30) begin
case (rel_f)
0: char = "F";
1: char = "R";
2: char = "M";
3: char = ":";
4: char = " ";
5: char = hex_char;
6: char = hex_char;
7: char = hex_char;
8: char = hex_char;
9: char = hex_char;
10: char = hex_char;
11: char = hex_char;
12: char = hex_char;
default: char = 0;
endcase
if (rel_f >= 0 && rel_f <= 12)
foreground_color = 24'h00FF66;
end
// ---- Footer "YOSYS + SV = LOVE" on row 56 ---------------
if (row == 56) begin
case (col - 32)
0: char = "Y";
1: char = "O";
2: char = "S";
3: char = "Y";
4: char = "S";
5: char = " ";
6: char = "+";
7: char = " ";
8: char = "S";
9: char = "V";
10: char = " ";
11: char = "=";
12: char = " ";
13: char = "L";
14: char = "O";
15: char = "V";
16: char = "E";
default: char = 0;
endcase
if ((col - 32) >= 0 && (col - 32) < 17)
foreground_color = {8'hFF, t, t};
end
end
// -------------------------------------------------------------
// UART beacon: send "** FPGA PLASMA DEMO ** Frame=XXXXXXXX\r\n"
// -------------------------------------------------------------
// 42 bytes total
localparam int MSG_LEN = 42;
logic [5:0] msg_idx = '0;
logic sending = 1'b0;
logic [23:0] throttle = '0;
logic [31:0] sent_frame = '0;
logic [7:0] msg_byte;
logic [3:0] nib;
always_comb begin
nib = 4'h0;
case (msg_idx)
6'd0: msg_byte = "*";
6'd1: msg_byte = "*";
6'd2: msg_byte = " ";
6'd3: msg_byte = "F";
6'd4: msg_byte = "P";
6'd5: msg_byte = "G";
6'd6: msg_byte = "A";
6'd7: msg_byte = " ";
6'd8: msg_byte = "P";
6'd9: msg_byte = "L";
6'd10: msg_byte = "A";
6'd11: msg_byte = "S";
6'd12: msg_byte = "M";
6'd13: msg_byte = "A";
6'd14: msg_byte = " ";
6'd15: msg_byte = "D";
6'd16: msg_byte = "E";
6'd17: msg_byte = "M";
6'd18: msg_byte = "O";
6'd19: msg_byte = " ";
6'd20: msg_byte = "*";
6'd21: msg_byte = "*";
6'd22: msg_byte = " ";
6'd23: msg_byte = "F";
6'd24: msg_byte = "r";
6'd25: msg_byte = "a";
6'd26: msg_byte = "m";
6'd27: msg_byte = "e";
6'd28: msg_byte = "=";
6'd29: begin msg_byte = 8'h00; nib = sent_frame[31:28]; end
6'd30: begin msg_byte = 8'h00; nib = sent_frame[27:24]; end
6'd31: begin msg_byte = 8'h00; nib = sent_frame[23:20]; end
6'd32: begin msg_byte = 8'h00; nib = sent_frame[19:16]; end
6'd33: begin msg_byte = 8'h00; nib = sent_frame[15:12]; end
6'd34: begin msg_byte = 8'h00; nib = sent_frame[11:8]; end
6'd35: begin msg_byte = 8'h00; nib = sent_frame[7:4]; end
6'd36: begin msg_byte = 8'h00; nib = sent_frame[3:0]; end
6'd37: msg_byte = "!";
6'd38: msg_byte = "\r";
6'd39: msg_byte = "\n";
default: msg_byte = 8'h00;
endcase
if (msg_idx >= 6'd29 && msg_idx <= 6'd36) begin
if (nib < 4'd10)
msg_byte = 8'h30 + {4'b0, nib};
else
msg_byte = 8'h41 + {4'b0, nib} - 8'd10;
end
uart_data = msg_byte;
uart_valid = sending && (msg_idx < MSG_LEN[5:0]);
end
always_ff @(posedge clk) begin
if (vsync == 1'b0 && old_vsync == 1'b1) begin
frame_counter <= frame_counter + 1;
end
old_vsync <= vsync;
if (sending) begin
if (uart_ready && uart_valid) begin
if (msg_idx == MSG_LEN[5:0] - 1) begin
sending <= 1'b0;
msg_idx <= '0;
end else begin
msg_idx <= msg_idx + 1;
end
end
end else begin
throttle <= throttle + 1;
if (throttle[22] == 1'b1) begin
sending <= 1'b1;
throttle <= '0;
sent_frame <= frame_counter;
end
end
end
endmodule
#FPGA #Icepi-Zero #HDL #SystemVerilog
Habr
Icepi Zero Bot
JCM
Jakub Cabal
Habr 25+
