Sometimes the wrong palette turns out right.
FPGA, RISC-V, 68K, OS, graphics, demos, permacomputing
| Project F | https://projectf.io |
| SystemTalk | https://systemtalk.org |
| omg.lol | https://flux.omg.lol |
Flux
@WillFlux
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Only hardware makes it possible!
FPGA, RISC-V, 68K, OS, graphics, demos, permacomputing
FPGA, RISC-V, 68K, OS, graphics, demos, permacomputing
Verilog error message of the day: "Illegal character in binary constant: 2". Yes, I'm appalled at myself too.
gojimmypiPublished my Radiona ULX3S FPGA HDMI Enclosure today!
https://github.com/gojimmypi/ulx3s-elecrow-7inch-hdmi-enclosure
Luke Wren
The drawing engine refactor was getting chunky, so I merged it. If you want to have a play, there are a few (not enough) details on the 🏝️ Isle.Computer blog: https://projectf.io/isle/2d-drawing.html
This refactor will allow me to share vram between CPU and drawing engine for the first Isle release. #FPGA
Matt VennAnnouncing the second Tiny Tapeout demoscene competition!
Free silicon space for all entrants!
https://tinytapeout.com/competitions/demoscene-ttsky26a-announce/
Too tired to sleep? Refactor Verilog 😴
Tonight, I removed the cross product from triangle rendering. This week's refactor added output enable, removed the need for two multipliers (MULT18X18D), reduced the lines of Verilog by 40, and increased max ECP5 frequency from 85 to 125 MHz.
Fast fills still to do. 🙃
Oni
Tonight's little 2D engine work simplified internal enable and status signals removing 78 lines of Verilog.
8 files changed, 61 insertions(+), 139 deletions(-)
Next up is tacking cross product removal from triangle rendering.
The 2D graphics engine has grown dynamically. Several areas need work, but they interact, which makes them hard to tackle. Now that I've done enable, I plan to tackle internal shape enable, remove the cross product, and support writing multiple pixels simultaneously (speeding up fills by up to 32x).