OniLucky enough to meet the Cairngorm reindeer today #scotland
FPGA, RISC-V, 68K, OS, graphics, demos, permacomputing
| Project F | https://projectf.io |
| SystemTalk | https://systemtalk.org |
| omg.lol | https://flux.omg.lol |
Flux
@WillFlux
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Only hardware makes it possible!
FPGA, RISC-V, 68K, OS, graphics, demos, permacomputing
FPGA, RISC-V, 68K, OS, graphics, demos, permacomputing
Tonight's little 2D engine work simplified internal enable and status signals removing 78 lines of Verilog.
8 files changed, 61 insertions(+), 139 deletions(-)
Next up is tacking cross product removal from triangle rendering.
The 2D graphics engine has grown dynamically. Several areas need work, but they interact, which makes them hard to tackle. Now that I've done enable, I plan to tackle internal shape enable, remove the cross product, and support writing multiple pixels simultaneously (speeding up fills by up to 32x).
I'm considering moving my git repos to #Codeberg (from GitHub). If you have open source projects on Codeberg, I'd be interested to learn from your experience. I host my own web sites, so it's only the core git stuff I need to worry about. 🙏
mole99A Tiny FABulous FPGA on Tiny Tapeout? It's more likely than you think!
Yesterday the TTIHP26a shuttle (https://app.tinytapeout.com/shuttles/ttihp26a) from #TinyTapeout has closed. In it, hundreds of incredible projects.
You can view the full shuttle and its designs here: https://app.tinytapeout.com/projects/3744
I had the opportunity to submit an FPGA, which I created using my FABulous LibreLane plugin. For this fabric, I developed a "tiny" tile library that better fits the constraints of Tiny Tapeout.
I've just updated 🏝️Isle chapter 6 software. It's exciting to work on big designs and graphics engines, but building a usable computer is about the small things too. #FPGAFriday
You can find the source code on GitHub (I'm considering moving to Codeberg): https://github.com/projf/isle
Includes everything you need for:
* @machdyne Lakritz (Lattice ECP5)
* Digilent Nexys Video (Xilinx XC7)
* Radiona #ULX3S (Lattice ECP5)
* Verilator simulator with SDL (Linux/macOS/Windows)
Sometimes you need to ship it and call it a night, so I give you 🏝️ Isle.Computer Chapter 6 - Input Output: https://projectf.io/isle/input-output.html
Adds input hardware, uart, Isle edition of FemtoRV "Gracilis" RV32IMC CPU, software library in #riscv asm, Verilator/SDL sim improvements... #FPGA
