Mastodawn

Good read on #VHDL’s delta cycle algorithm in action. Delta cycles are an #HDL concept used to order events that occur in zero physical time:

VHDL's crown jewel

https://www.sigasi.com/opinion/jan/vhdls-crown-jewel/

VHDL's crown jewel

How VHDL preserves determinism In this post, I would like to talk about VHDL’s crown jewel: how it preserves determinism in a concurrent language. Here is a figure of how it works:

Sigasi

GripNews 5d ago

🌘 VHDL 的核心瑰寶：論其如何維護確定性
➤ 從 Delta Cycle 看 VHDL 與 Verilog 的本質區別
✤ https://www.sigasi.com/opinion/jan/vhdls-crown-jewel/
本文深入剖析了硬體描述語言（HDL）中一個關鍵的設計哲學差異。作者將 VHDL 的「Delta Cycle」（增量週期）演算法譽為該語言的皇冠明珠，並解釋了為何該機制能確保模擬結果的確定性。相較之下，Verilog 因缺乏類似的嚴格分階段處理機制，導致在處理併發事件時容易出現非確定性的結果。作者認為，VHDL 通過將信號更新與流程評估強制分離，以極低的成本解決了併發設計中的核心問題。
+ 這篇文章精準地擊中了 Verilog 使用者的痛點。非阻塞賦值的確經常被誤用，而 VHDL 的這種嚴謹性確實讓大型複雜系統的模擬更具可靠性。
+ 很喜歡這種深入底層邏輯的分析。雖然現在 EDA 工具越來越強大，但理解 Delta Cycle 對於除錯模擬中的奇異現象（race conditions）仍然至
#HDL 設計 #VHDL #Verilog #數位電路模擬

VHDL's crown jewel

How VHDL preserves determinism In this post, I would like to talk about VHDL’s crown jewel: how it preserves determinism in a concurrent language. Here is a figure of how it works:

Sigasi

PipelineC Mar 28

Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how?

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Video-Pipelines

#hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

PipelineC Mar 28

Fun in the frequency domain 🤓 Camera pointed at it's own display also showing audio FFT for cool glitchy visualizer effect. Video processing all done in PipelineC hardware. And how? github.com/JulianKemmer... #hardware #fpga #dsp #rtl #hdl #hls #verilog #vhdl #pipelinec

Gray Beard Mar 27

SystemLisp - an HDL simulator written in Common Lisp

https://github.com/systemlisp

#lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga

systemlisp - Overview

An experimental HDL simulator written in Common Lisp focused on interactive and extensible hardware design and verification. - systemlisp

GitHub

PipelineC Mar 13

@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓 github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

PipelineC Mar 13

@nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks 🤓

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

PipelineC Mar 10

PipelineC holds the throughput lead on Latchup.app. For now! How does your design stack up against a pipelining tool? Far too time consuming and fun of a site 🤓 Look forward to seeing competing solutions. github.com/JulianKemmer... #fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

PipelineC Mar 10

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Latchup-Solutions

#fpga #asic #rtl #hdl #verilog #vhdl #hls #eda

Icepi Zero Bot Mar 7

@[email protected] asked

Sucess!

UtilizationCellUsedAvailableUsage DCCA2563.6% EHXPLLL1250% MULT18X18D32810.7% TRELLIS_COMB125052428851.5% TRELLIS_FF145242880.6% TRELLIS_IO101975.1% TRELLIS_RAMW1200303639.5%
TimingClockAchievedConstraint $glbnet$clkp31.01 MHz25 MHz $glbnet$clkt277.32 MHz250 MHz
Code

module my_code #(
parameter int WIDTH = 640,
parameter int HEIGHT = 480,
parameter int CONSOLE_COLUMNS = WIDTH / 8,
parameter int CONSOLE_ROWS = HEIGHT / 8
)(
input logic clk,
input logic rst,
input int px,
input int py,
input logic hsync,
input logic vsync,
input int col,
input int row,
output int char,
output logic [23:0] foreground_color,
output logic [23:0] background_color
);
// version 2.0
// Fire resolution: 80x60 â scaled to 640x480
localparam int FW = 80;
localparam int FH = 60;
logic [7:0] fire[FH-1:0][FW-1:0];
logic old_vsync;
logic [7:0] lfsr;
// length of div slows frequency of sparks
logic [4:0] spark_div;
logic updating;
logic [6:0] ux;
logic [5:0] uy;
assign char = 0;
assign foreground_color = 24'hFFFFFF;
// Scale VGA pixel to fire coordinates
wire [6:0] fx = px[9:3]; // /8 â 0..79
wire [5:0] fy = py[9:3]; // /8 â 0..59
wire [7:0] v = fire[fy][fx];
// Map intensity to flame color: red dominant, green half, blue low
assign background_color = {v, v >> 1, v >> 3};
integer x,y;
always_ff @(posedge clk) begin
if (rst) begin
old_vsync <= 0;
updating <= 0;
ux <= 0;
uy <= 0;
spark_div <= 0;
lfsr <= 8'hA5;
// for (y=0; y<FH; y=y+1)
// for (x=0; x<FW; x=x+1)
// fire[y][x] <= 0;
end else begin
// start update on vsync rising edge (enter VBLANK)
if (vsync && !old_vsync) begin
updating <= 1;
ux <= 0;
uy <= 0;
end
// scroll fire upward across many clocks
if (updating) begin
// slight decay based on lsb of x coordinate times 2
fire[uy][ux] <= fire[uy+1][ux] - (ux & 1)<<1;
if (ux == FW-1) begin
ux <= 0;
if (uy == FH-2) begin
updating <= 0;
uy <= 0;
end else begin
uy <= uy + 1;
end
end else begin
ux <= ux + 1;
end
end
// bottom sparks (slow, only when not updating)
if (vsync && !old_vsync && !updating) begin
spark_div <= spark_div + 1;
if (!spark_div) begin
lfsr <= {lfsr[6:0],
lfsr[7]^lfsr[5]^lfsr[4]^lfsr[3]};
fire[FH-1][lfsr[6:0]] <= 8'hFF;
end
end
old_vsync <= vsync;
end
end
endmodule

#FPGA #Icepi-Zero #HDL #SystemVerilog