PipelineC6d ago
@nlnetlabs.bsky.social NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks πŸ€“ github.com/JulianKemmer... #hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec
PipelineC6d ago

@nlnet NLnet Foundation funded open source WireGuard router in FPGA. Featuring PipelineC for cryptography blocks πŸ€“

https://github.com/JulianKemmerer/PipelineC/wiki/Example:-ChaCha20%E2%80%90Poly1305-for-WireGuard

#hardware #fpga #rtl #hdl #hls #verilog #vhdl #cryptography #wireguard #pipelinec

PipelineCJan 1

Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎

https://github.com/JulianKemmerer/PipelineC/blob/master/examples/aof25/day7.c

#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

PipelineC/examples/aof25/day7.c at master Β· JulianKemmerer/PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. - JulianKemmerer/PipelineC

GitHub
PipelineCJan 1
Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

github.com/JulianKemmerer...
PipelineC/examples/aof25/day7.c at master Β· JulianKemmerer/PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. - JulianKemmerer/PipelineC

GitHub
PipelineCMar 14, 2025
Check out @dutracgi 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL !
#dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware https://www.linkedin.com/pulse/16-apsk-modulator-fpga-using-pipelinec-hdl-paulo-dutra-79uce/?trackingId=ldQbwhDmRd%2BU7F35jVGjAQ%3D%3D
16-APSK Modulator on FPGA using PipelineC HDL

Introduction Amplitude and Phase Shift Keying (APSK) is a modulation technique used in Radio frequency (RF) systems that combine two existing techniques: ASK (Amplitude shift keying) and PSK (Phase shift keying), the first encodes data as amplitude (voltage) changes on the signal, and the second enc

Show threadPipelineCNov 30, 2024
Come on over to the Discord channel if you want to join the conversation about this fun work πŸ€“ https://discord.gg/vBUtmBZcxC #FPGA #raspberrypi #pico-ice #PipelineC #HDL #Verilog #VHDL
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PipelineCNov 30, 2024
Have been super pleased with the #ice40 #FPGA and #raspberrypi board that https://pico-ice.tinyvision.ai/ sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice πŸ€“ #HDL #Verilog #VHDL #hardware #embedded
pico-ice: Main Page

PipelineCJul 25, 2024
Over at Digital Design HQ #ddhq, I'm documenting and discussing a #hardware #FPGA #I2S #audio #pmod to-from #AXI project. Stop on by πŸ‘‹ and see how nice it is to work in #PipelineC πŸ€“ #RTL #HDL #HLS https://discord.gg/ceheSfKzRM
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PipelineCJul 20, 2024
#graphics #demoscene folks: What's possible with just a few hundred bits of memory? Make custom #ASIC #hardware. #PipelineC friends @suarezvictor and @dutracgi have done LARGE #FPGA demos in the past. Now the challenge is to be very SMALL! πŸ€“
https://tinytapeout.com/competitions/demoscene/
Demoscene - Tiny Tapeout

Build a sound and graphics demo in less than 161 x 225 microns of 130nm ASIC

Quicker, easier and cheaper to make your own chip!
PipelineCJun 1, 2024
Anyone want to help make a #PipelineC version of @DG3YEV 's #FPGA real time #FFT display but for audio? Have Arty w/ #pmod ready to go for testing. Picturing the start of some kind of #hardware #audio visualizer 🀩 with more #DSP learning along the way πŸ€“
https://x.com/Dg3Yev/status/1796857709276373211
DG3YEV Tobias (@Dg3Yev) on X

2400 - 2440 MHz. You yee my phone perforing a speedtest. Obviously it only gets to use 20MHz channel bandwidth because of mediocre link quality.

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