Om voor meer inspiratie te zorgen voor zijn plantaardige keuken, liet chef Pieter-Jan Lint van restaurant #Amaranth een #pluktuin aanleggen met tientallen eetbare planten en kruiden.🌱👌💚

https://www.nieuwsblad.be/regio/oost-vlaanderen/regio-gent/merelbeke-melle/eigen-pluktuin-doet-chef-pieter-jan-39-al-dromen-van-nieuwe-plantaardige-gerechten-koken-zal-niet-meer-in-de-keuken-beginnen/156528183.html

@[email protected]

I am pleased to announce that @icepi-zero-bot is back up and running. 

Now inside my Kubernetes cluster on more powerful hardware, so you should hopefully see some faster synthesis times and slightly nicer videos!
I think I secured it pretty well, but if someone manages to do something naughty, please don't nom-nom all my data :pleading_face:
Also, please don't break my FPGA on purporse, oki? :3

Sadly, I still need to figure out Spade support, because I couldn't find any prebuilt arm64 binaries for it :(

So, if you want to write cool SystemVerilog/VHDL/Amaranth/Veryl code, have it run on a real FPGA and output video (no need to implement DVI yourself, dw), which is then recorded and posted, check out @icepi-zero-bot's profile! The profile description contains tons of explanations and templates.

Soon, I will hopefully add Spade support back and also implement a UART interface, so you can also output text! The support for that in the bot is already there, I just need to implement a UART transmitter in VHDL and think of a cute and easy interface.

Edit: PRELEKCJA ODWOŁANA.
Niestety z powodów zdrowotnych prelegentka była zmuszona odwołać swój przyjazd. Dziękujemy za wyrozumiałość i życzymy zdrowia!
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⚡ Gateware może być przyjemny – o DSLu i transakcyjnym sprzęcie

@ariac z @coreforge pokaże, że projektowanie #FPGA nie musi być bolesne. Na przykładzie prostego procesora #RISCV poznacie #Amaranth – oparty na Pythonie język opisu sprzętu – oraz bibliotekę #Transactron.

#piwo2026

my upcoming FPGA dev board "#bare_metal".

most tests are done, most changes and bugfixes are in this V2. not sure when I got time for a "tapeout" ;)

- 16x8 SPI based RGB LED display
- single PMOD interface
- OK button and D-pad
- USB bootloader
- 3 user bitstreams by default, extendable to dozens
- LiPo battery with protection and management
- comes with a PCB stand
- PCB stand comes with pinout tables

#FPGA #bare_metal #yosys #nextpnr #verilog #amaranth #spade #HDL #nametag

made some progress over the weekend on #amaranth companion

the code in the blocks now gets executed and the number of input and output sockets changes accordingly

First amaranth leaf salad of the year. Amaranth is an underrated salad 'greens' (reds) plant in areas too hot for lettuce for much of the year.

We leave most of the grains for the chickens and as seeds for the following year.

Last year, we watered two plants, the rest had to fend for themselves. Those two grew to over 6 feet and got so top heavy they had to be tied down.

#food #grain #vegetable #DroughtTolerant #amaranth

definitely it's alive.

#FPGA #rainbow #bare_metal #ice40 #up5k #verilog #vhdl #amaranth #yosys #nextpnr #clarie