my upcoming FPGA dev board "#bare_metal".

most tests are done, most changes and bugfixes are in this V2. not sure when I got time for a "tapeout" ;)

- 16x8 SPI based RGB LED display
- single PMOD interface
- OK button and D-pad
- USB bootloader
- 3 user bitstreams by default, extendable to dozens
- LiPo battery with protection and management
- comes with a PCB stand
- PCB stand comes with pinout tables

#FPGA #bare_metal #yosys #nextpnr #verilog #amaranth #spade #HDL #nametag

Встреча FPGA-сообщества: онлайн, вечер, пять докладов

Регулярный слет сообщества FPGA-инженеров и им причастных пройдет 26 мая в 19 часов в формате онлайн-трансляции. В программе вечера пять докладов: о Yosys, SystemRDL, Edge AI и анализе вейвформ с LLM. Подробности о темах и спикерах — под катом. А регистрация —

https://habr.com/ru/companies/yadro/articles/1034776/

#fpga #митап #yosys #systemrdl #edgeai

definitely it's alive.

#FPGA #rainbow #bare_metal #ice40 #up5k #verilog #vhdl #amaranth #yosys #nextpnr #clarie

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

This week experimented with adding a matmul & sorting accelerators (and opcodes for both) to PicoRV32 using the PCPI interface. Also added support for those ops to the Spike RISCV simulator. Yes, Claude helped a huge amount with these tasks which would've likely taken weeks otherwise. The design simulates (Verilator) & sythesizes (yosys) and I can generate a bitstream for both GateMateA1 and ECP5 (OrangeCrab board)

#FPGA #yosys #verilator

time will tell...

#fpga #bare_metal #ice40 #ice40up5k #yosys

Gee!
ADC went through #yosys and #nextpnr!

Does it work on hardware? Absolutely not!🤣
#apicula#fpga#gowin#sipeed

This is a wiki about processing video in real time using microcontrollers, ASICs and FPGAs. The related paper was accepted for the Open Source Hardware Conference in Chemnitz Germany, Nov 24-25 2025.

Comment on the page by replying to this toot. #Introduction

#OSHOP #OpenSource #Hardware #FPGA #Yosys #Nextpnr #Video #Pipelines #Introduction

https://wiki.pythonlinks.info/video

Fully #freesoftware based support for GateMate FPGAs from Cologne Chip [0] just landed in #guix.

It includes #yosys for synthesis, #openFPGALoader for device flashing and #nextpnr for placement and routing.

guix shell -C -m manifest.scm -- make

The whole toolchain runs in a #sourcehut #ci pipeline.

https://builds.sr.ht/~csantosb/job/1588460#task-test

[0] https://indico.cern.ch/event/1587509 for details on #gatemate #fpga.