I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).
It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.
I highly recommend it! It's so much fun!
You can make your own SoC with deranged peripherals!
This week experimented with adding a matmul & sorting accelerators (and opcodes for both) to PicoRV32 using the PCPI interface. Also added support for those ops to the Spike RISCV simulator. Yes, Claude helped a huge amount with these tasks which would've likely taken weeks otherwise. The design simulates (Verilator) & sythesizes (yosys) and I can generate a bitstream for both GateMateA1 and ECP5 (OrangeCrab board)
Gee!
ADC went through #yosys and #nextpnr!
Does it work on hardware? Absolutely not!🤣
#apicula#fpga#gowin#sipeed
This is a wiki about processing video in real time using microcontrollers, ASICs and FPGAs. The related paper was accepted for the Open Source Hardware Conference in Chemnitz Germany, Nov 24-25 2025.
Comment on the page by replying to this toot. #Introduction
#OSHOP #OpenSource #Hardware #FPGA #Yosys #Nextpnr #Video #Pipelines #Introduction
Fully #freesoftware based support for GateMate FPGAs from Cologne Chip [0] just landed in #guix.
It includes #yosys for synthesis, #openFPGALoader for device flashing and #nextpnr for placement and routing.
guix shell -C -m manifest.scm -- make
The whole toolchain runs in a #sourcehut #ci pipeline.
https://builds.sr.ht/~csantosb/job/1588460#task-test
[0] https://indico.cern.ch/event/1587509 for details on #gatemate #fpga.
@guix Other than as package manager on top of #archlinux, I’m using #guix for electronics design, mostly #vhdl and #fpga related stuff.
I run simulations with help of #hdlmake using #ghdl compiler, #osvvm for verification, #cocotb for testbenches, #yosys for synthesis, #nextpnr for placement and routing and #openFPGALoader for flashing. Finally, I use my own Guix channel to package gateware and run #ci tests on #sourcehut Guix image. A demo toy example of this runs here
One step closer to UNIX v1 using open source toolchain: https://github.com/YosysHQ/yosys/pull/5411
News about GW5 series - PLL went through #yosys, #nextpnr, and #apicula and started working!🍾
At the moment, there are a huge number of crutches, which I plan to remove in the near future and make the appropriate PR.😉 #fpga#gowin#sipeed
@PaulaMaddox Well, I've got the gui tool installed and I see I can start with a demo that echoes data back via the Ft+ V2... that seems like a great start.
Crossing fingers.
I'm not worried about an upload tool much. More about design lock in or other anti-patterns.
I'd love to get experience with #yosys and #nextpnr and maybe this will be my excuse to try.
HP van Braam
philtor 🇺🇦🌻
wenzellabs
YRabbit
Video Processing Wiki
Cayetano Santos
plaes
poleguy looking for lost tools