YRabbitThe HCLK in the GW5A series is a bit of a mystery. But in any case, #Apicula supports the first serializer—OSER4—and does so right through the entire chain, all the way to the hardware.#fpga#gowin#sipeed
@WillFlux Um... not so fast :)
I will bring #Tangmega138k support in #apicula to a state where some #riscv will run, but then I will need to go back to GW5A-25A and focus on DSP and serial IO.
At this point, there won't be a PLL support to run #isle. I hope someone will join in and implement PLL :)
But in any case, #isle will be launched on 138 this year, as I promised.😉
yes! ADC - #apicula -syle 🤣
The blue LEDs are service signals (readiness, counters, etc.), while the top two bars represent ADC measurement data, with the least significant bits at the top.
There is still a lot of work ahead - for starters, I pulled out the SDRAM not because I wanted to, but because the ADC is very picky about which pins it can listen to.
#fpga#gowin#sipeed
Classic Wizardry on #sipeed #Tangprimer25k!
Just kidding.🤣
The frame is a background image, but the maze itself and the strange spherical creature are the work of the @WillFlux 's 2D accelerator!
I'm doing this out of pure interest to check the accuracy of #apicula and #nextpnr on the GW5 series of #gowin #fpga
Gee!
ADC went through #yosys and #nextpnr!
Does it work on hardware? Absolutely not!🤣
#apicula#fpga#gowin#sipeed
TangPrimer25k beeps the initial sequence and 3-4 lines of the image from the screen. I am within the 2000Hz-4000Hz range for recording on an audio cassette, although there is no connection block with a tape recorder line input yet - as I wrote earlier, this PMOD is somewhat ill-conceived.🤣
I hope @WillFlux doesn't mind that I used the edges of the screen in his video subsystem like this.😉
Gee! All 64M, which are organised into these two chips with a 16-bit common bus, are written, read and, most importantly, refreshed normally.
I can only use 22 bits for direct addressing, so all this goodness is organised as 16 pages of 4M each.🤣 #apicula#fpga#sipeed#gowin
The main problem with BSRAM initialisation is not placing the bits in the right place (this is easily detected after a couple of comparisons of compiled black-and-white images as data for BSRAM), but correctly calculating the CRC.
The img shows the streams after #Apicula and after IDE. The two CRC bytes before the long sequence 1 do not match. This means that I either did not take something into account, took something extra, or did not initialise the the CRC calculation correctly🤪
#fpga#gowin
The img shows the streams after #Apicula and after IDE. The two CRC bytes before the long sequence 1 do not match. This means that I either did not take something into account, took something extra, or did not initialise the the CRC calculation correctly🤪
#fpga#gowin
