YRabbitThe original signal is 2.98 Hz, divided by 2 and then by 5—0.298 Hz, divided by 2 and then by 3.5—0.42571 Hz.
#Apicula has learned to divide by all sorts of numbers by combining the CLKDIV2 and CLKDIV primitives🤣 #fpga
The HCLK in the GW5A series is a bit of a mystery. But in any case, #Apicula supports the first serializer—OSER4—and does so right through the entire chain, all the way to the hardware.#fpga#gowin#sipeed
@WillFlux Um... not so fast :)
I will bring #Tangmega138k support in #apicula to a state where some #riscv will run, but then I will need to go back to GW5A-25A and focus on DSP and serial IO.
At this point, there won't be a PLL support to run #isle. I hope someone will join in and implement PLL :)
But in any case, #isle will be launched on 138 this year, as I promised.😉
yes! ADC - #apicula -syle 🤣
The blue LEDs are service signals (readiness, counters, etc.), while the top two bars represent ADC measurement data, with the least significant bits at the top.
There is still a lot of work ahead - for starters, I pulled out the SDRAM not because I wanted to, but because the ADC is very picky about which pins it can listen to.
#fpga#gowin#sipeed
Classic Wizardry on #sipeed #Tangprimer25k!
Just kidding.🤣
The frame is a background image, but the maze itself and the strange spherical creature are the work of the @WillFlux 's 2D accelerator!
I'm doing this out of pure interest to check the accuracy of #apicula and #nextpnr on the GW5 series of #gowin #fpga
