Success!
UtilizationCellUsedAvailableUsage
DCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB417242881.7%TRELLIS_FF128242880.5%TRELLIS_IO111975.6%TimingClockAchievedConstraint
$glbnet$clkp130.92 MHz25 MHz$glbnet$clkt374.53 MHz250 MHzCode
#[no_mangle(all)]
entity my_code(
clk: clock,
rst: bool,
px: int<32>,
py: int<32>,
hsync: bool,
vsync: bool,
col: int<32>,
row: int<32>,
char: inv &int<32>,
foreground_color: inv &uint<24>,
background_color: inv &uint<24>,
uart_data: inv &uint<8>,
uart_ready: bool,
uart_valid: inv bool,
) {
set char = &87;
set foreground_color = &0xFFFFFFu24;
set background_color = &0xFF7AFFu24;
set uart_data = &0x00;
set uart_valid = &false;
}
#FPGA #Icepi-Zero #HDL #Spade




