So, I made 8 FlipFlops and placed them in each of the 8 quadrants of #Tangmega138k #fpga. Each DFF is connected to its own LED and transmits the button status to it.
#nextpnr successfully routed through the central bridge to all 8 quadrants.
gowin_pack wrote all the fuses and, in addition, 9 special ones for clock enabling in the quadrants and bridge.
So. It's a happy day - #nextpnr has successfully dealt with that terror that claps in the night, known as the βclock system in the GW5A seriesβ!π€£
It definitely won't work in hardware because we still need to find and install a bunch of fuses responsible for this switching, but the most important thing has been done β the topology has been described in such a way that #nextpnr can search for the correct routes:)
I'll take a short break to test the motherboard in a 3D printer.
#fpga#apicula
Classic Wizardry on #sipeed #Tangprimer25k!
Just kidding.π€£
The frame is a background image, but the maze itself and the strange spherical creature are the work of the @WillFlux 's 2D accelerator!
I'm doing this out of pure interest to check the accuracy of #apicula and #nextpnr on the GW5 series of #gowin #fpga
Gee!
ADC went through #yosys and #nextpnr!
Does it work on hardware? Absolutely not!π€£
#apicula#fpga#gowin#sipeed
This is a wiki about processing video in real time using microcontrollers, ASICs and FPGAs. The related paper was accepted for the Open Source Hardware Conference in Chemnitz Germany, Nov 24-25 2025.
Comment on the page by replying to this toot. #Introduction
#OSHOP #OpenSource #Hardware #FPGA #Yosys #Nextpnr #Video #Pipelines #Introduction
Gee! When compiling in the vendor IDE, I unexpectedly got about two dozen elements around the BSRAM that are not in the design. I traced all the wires and now I figured out what it is - it's an address decoder that repeats all the functionality of the internal BSRAM decoder, but only for one address pin ADB4. And it replicates all the quirks β a delay cycles, manual decoding of BLKSEL signals, etc.
Great! Now I can replicate this in #nextpnr and users won't have to worry about this crap.
#fpga
Fully #freesoftware based support for GateMate FPGAs from Cologne Chip [0] just landed in #guix.
It includes #yosys for synthesis, #openFPGALoader for device flashing and #nextpnr for placement and routing.
guix shell -C -m manifest.scm -- make
The whole toolchain runs in a #sourcehut #ci pipeline.
https://builds.sr.ht/~csantosb/job/1588460#task-test
[0] https://indico.cern.ch/event/1587509 for details on #gatemate #fpga.
@guix Other than as package manager on top of #archlinux, Iβm using #guix for electronics design, mostly #vhdl and #fpga related stuff.
I run simulations with help of #hdlmake using #ghdl compiler, #osvvm for verification, #cocotb for testbenches, #yosys for synthesis, #nextpnr for placement and routing and #openFPGALoader for flashing. Finally, I use my own Guix channel to package gateware and run #ci tests on #sourcehut Guix image. A demo toy example of this runs here
YRabbit
Video Processing Wiki
Cayetano Santos