my upcoming FPGA dev board "#bare_metal".

most tests are done, most changes and bugfixes are in this V2. not sure when I got time for a "tapeout" ;)

- 16x8 SPI based RGB LED display
- single PMOD interface
- OK button and D-pad
- USB bootloader
- 3 user bitstreams by default, extendable to dozens
- LiPo battery with protection and management
- comes with a PCB stand
- PCB stand comes with pinout tables

#FPGA #bare_metal #yosys #nextpnr #verilog #amaranth #spade #HDL #nametag

definitely it's alive.

#FPGA #rainbow #bare_metal #ice40 #up5k #verilog #vhdl #amaranth #yosys #nextpnr #clarie

I've been playing around with #LiteX and #migen #HDL lately and I think it's finally starting to sink in that you can really just do almost arbitrary amounts of "stuff" per clock (limitations apply, objects in mirror may appear closer etc).

It's really very fun! And between trellis, #yosys and #nextpnr you can just... Do it without begging any vendor for a free copy of an EDA.

I highly recommend it! It's so much fun!

You can make your own SoC with deranged peripherals!

#electronics #fpga

#nextpnr release! 🍾

https://github.com/YosysHQ/nextpnr/releases/tag/nextpnr-0.10

So, I made 8 FlipFlops and placed them in each of the 8 quadrants of #Tangmega138k #fpga. Each DFF is connected to its own LED and transmits the button status to it.

#nextpnr successfully routed through the central bridge to all 8 quadrants.

gowin_pack wrote all the fuses and, in addition, 9 special ones for clock enabling in the quadrants and bridge.

So. It's a happy day - #nextpnr has successfully dealt with that terror that claps in the night, known as the ‘clock system in the GW5A series’!🤣

It definitely won't work in hardware because we still need to find and install a bunch of fuses responsible for this switching, but the most important thing has been done — the topology has been described in such a way that #nextpnr can search for the correct routes:)

I'll take a short break to test the motherboard in a 3D printer.
#fpga#apicula

Classic Wizardry on #sipeed #Tangprimer25k!

Just kidding.🤣

The frame is a background image, but the maze itself and the strange spherical creature are the work of the @WillFlux 's 2D accelerator!

I'm doing this out of pure interest to check the accuracy of #apicula and #nextpnr on the GW5 series of #gowin #fpga

Gee!
ADC went through #yosys and #nextpnr!

Does it work on hardware? Absolutely not!🤣
#apicula#fpga#gowin#sipeed

This is a wiki about processing video in real time using microcontrollers, ASICs and FPGAs. The related paper was accepted for the Open Source Hardware Conference in Chemnitz Germany, Nov 24-25 2025.

Comment on the page by replying to this toot. #Introduction

#OSHOP #OpenSource #Hardware #FPGA #Yosys #Nextpnr #Video #Pipelines #Introduction

https://wiki.pythonlinks.info/video

Gee! When compiling in the vendor IDE, I unexpectedly got about two dozen elements around the BSRAM that are not in the design. I traced all the wires and now I figured out what it is - it's an address decoder that repeats all the functionality of the internal BSRAM decoder, but only for one address pin ADB4. And it replicates all the quirks — a delay cycles, manual decoding of BLKSEL signals, etc.

Great! Now I can replicate this in #nextpnr and users won't have to worry about this crap.
#fpga