Max KorbelJan 7

🚀 ROHD v0.6.7 released

• Cleaner generated RTL & SystemVerilog
• Faster simulation for glitchy conditionals
• Improved SSA & write-after-read error messages
• Better debugability and APIs

Learn more: https://intel.github.io/rohd-website/

Join the discussion: https://discord.gg/DfD2RuAzzh

#ROHD #HardwareDesign #SystemVerilog #EDA #OpenSource #RTL

ROHD

A better way to develop hardware. Star Count

ROHD
Max KorbelNov 1

🧠 Deep dive: “AI-Accelerated Agile Design Using the ROHD Framework”
How AI and ROHD combine for faster, more correct hardware design.
📝 https://intel.github.io/rohd-website/blog/ai-accelerated-agile-design/

💬 Join the ROHD Discord → https://discord.gg/DfD2RuAzzh

#AI #HardwareDesign #ROHD #Verilog #AgileHardware #OpenSource #EDA

Max KorbelOct 30

🚀 AI for hardware design is here.
Intel Sr. PE Desmond Kirkpatrick shows how LLMs and the ROHD framework enable agile, test-driven hardware development — for real synthesizable designs.
🎥 https://youtu.be/SAPAi8Y4Z68

#AI #Hardware #ROHD #OpenSourceHardware #EDA #VLSI #FPGA #Semiconductors

AI Accelerated Agile Design Using the ROHD Framework

YouTube
Max KorbelFeb 19, 2025

🚀 ROHD is now silicon-proven! 🎉

Our open-source hardware framework has officially made it to real silicon! This milestone proves that ROHD is more than just theory—it's powering real chips.

A huge thanks to everyone who contributed! 🏆

🔗 More details: https://intel.github.io/rohd-website/

#ROHD #FOSS #OpenSourceHardware #FPGA #ASIC #EDA

ROHD

A better way to develop hardware. Star Count

ROHD
Max KorbelFeb 12, 2025
It's pretty cool that my post on combinational logic in ROHD is in the top-3 results on Google when you search for `always_comb`! https://intel.github.io/rohd-website/blog/combinational-ssa/ #rohd #always_comb #SystemVerilog #dart #opensource
Procedural Combinational Logic, SystemVerilog’s always_comb, and SSA in ROHD

ROHD has recently gained a powerful new feature in the Combinational.ssa constructor for Combinationals that allows safer implementations of equivalent always_comb logic in SystemVerilog. This post discusses some of the motivations of the feature and highlights the power gained by using it.

ROHD
Max KorbelFeb 6, 2025
While it's disappointing that Dart macros are put on hold, I'm glad that features like augmentation are still planned. I think leveraging build_runner with augmentations could provide a lot! https://buff.ly/3Ei6JST #dart #rohd
An update on Dart macros & data serialization - Dart - Medium

We have invested significant time and resources to prototype macros over the past couple years. Unfortunately, each time we solved a major technical hurdle, we saw new ones pop up. At this point, we…

Dart
Max KorbelFeb 5, 2025
Exciting update for the ROHD community! We're pleased to announce the release of ROHD Cosim v0.3.0, now supporting in/out ports and Verilator for enhanced simulation. Also, ROHD v0.6.2 is out, featuring some bug fixes and improved adder syntax in SystemVerilog. https://buff.ly/3WLth4y #rohd #opensource #hardware #hdl #cosim #verilator
ROHD

A better way to develop hardware. Star Count

ROHD
Max KorbelFeb 2, 2025

👋 Hi, I’m Max! I’m an engineer passionate about both hardware & software. I'm a Principal Engineer at Intel helping to shape the future of hardware, and I lead the open-source ROHD project, making hardware development more accessible and fun.

I enjoy working on personal projects (especially with Dart), snowboarding 🏂, gaming 🎮, and exploring new tech.

Excited to connect with folks in open-source, hardware, and beyond! 🚀

#introduction #opensource #hardware #software #soc #fpga #dart #hdl #rohd