The irony: the entire RISC-V base ISA (RV64GC) is beautifully RISC: simple opcodes, fixed 32-bit instructions (+ compressed), load/store architecture, no flags, no implicit state. Then RVV comes along and throws all those principles out the window: global implicit state, microcode-like behavior, variable semantics of the same instruction.

Because vsetvli changes the semantics of all subsequent V-instructions based on the current VLEN configuration. For a JIT compiler in an Emulator and for an Emulator in general, this means having to continuously track the vtype state and react to any changes, a fundamental contradiction to the principle of statically analyzable instructions. It feels like the RISC-V Foundation sacrificed the simplicity and elegance of the RISC principle to create a powerful but extremely complex "super-SIMD" that is difficult to efficiently map in a JIT. A more traditional SIMD extension with fixed vector widths and clearly defined instruction semantics would have been much more JIT-friendly. The upcoming P extension does go in that direction, but it is primarily targeted at embedded and low-power applications rather than high-performance computing.

#riscv #riscv64 #emulation #pasriscv #object_pascal #delphi #free_pascal

🤸 updated #docker images for #duckdb v1.4.3
- based on Alpine: https://hub.docker.com/r/codieplusplus/duckdb
- based on Debian: https://hub.docker.com/r/codieplusplus/duckdb-debian

all multi-arch for #amd64, #arm64, #riscv64

codieplusplus/duckdb - Docker Image

It's 2026 now and time for an updated blog post for cross-compiling Chromium for RISC-V from scratch.

This blog post is much more simple compared with my previous blog post, because many RISC-V patches have been merged into Chromium mainline.

https://www.kxxt.dev/blog/cross-compile-chromium-for-riscv-2026/

#chromium #riscv #riscv64 #linux

Cross compile mainline Chromium for RISC-V from scratch (2026)

This blog post walks you through the procedures about cross compiling mainline chromium for riscv64 from the absolute scratch.

I have that page about Arm cpu cores and their features.

RISC-V cpus has insane amount of extensions. I wonder when someone will make similar page about their details.

https://gpages.juszkiewicz.com.pl/arm-socs-table/arm-cpu-cores.html

#riscv64 #riscv

AArch64 cpu core information table

AArch64 cpu core information table

Marcin Juszkiewicz

« Milk-V Titan : Powered by a 2 GHz UR-DP1000 octa-core RISC-V CPU, the Titan mini-ITX motherboard supports up to 64GB DIMM memory and M.2 NVMe storage (PCIe Gen4 x4), and features a PCIe Gen4 x16 slot for a graphics card or other expansion, Gigabit Ethernet, four USB 3.0 ports, a BMC, and more. »

https://www.cnx-software.com/2026/01/12/milk-v-titan-a-329-octa-core-64-bit-risc-v-mini-itx-motherboard-with-a-pcie-gen4-x16-slot/

#RISC #RISCV #RISCV64 #MiniITX #Motherboard #OpenSource

Milk-V Titan – A $329 octa-core 64-bit RISC-V mini-ITX motherboard with a PCIe Gen4 x16 slot

We first noted the UltraRISC UR-DP1000-powered Milk-V Titan mini-ITX motherboard when we wrote an article about three high-performance RISC-V processors to watch in H2 2025. There have been some delays, as there often are, but the Titan board finally appears to be in stock, so it's probably a good time to have a closer look. Powered by a 2 GHz UR-DP1000 octa-core RISC-V CPU, the Titan mini-ITX motherboard supports up to 64GB DIMM memory and M.2 NVMe storage (PCIe Gen4 x4), and features a PCIe Gen4 x16 slot for a graphics card or other expansion, Gigabit Ethernet, four USB 3.0 ports, a BMC, and more. Milk-V Titan specifications: CPU - UltraRISC UR-DP1000 8x 64-bit RISC-V UR-CP100 “RV64GCBHX” cores up to 2.0 GHz Two 4x core cluster design with 4MB L3 cache each, and a total of 16MB cache. Fully RVA22 compliant, and “Compliant with RVA23 excluding V extension.” Supports Hardware

CNX Software - Embedded Systems News

Happy new #BSD year?

Is there any BSD variant that will run on the Sipeed LicheePi Console?

See:
https://wiki.sipeed.com/hardware/en/lichee/th1520/lcon4a/lcon4a.html

I guess not, but what do I know?
Thanks in advance.

#runbsd #riscv64 #licheepiconsole

LicheePi Console 4A - Sipeed Wiki

PasRISCV now has its own local CLI debugger alongside the GDB remote server. It supports breakpoints, single-stepping, register & memory inspection, and allows simultaneous local CLI and remote GDB sessions. A public debugger API enables future graphical debugger frontends.

https://youtu.be/yznijHMKj_0

#riscv64 #riscv #emulation #pascal #object_pascal #debugger

PasRISCV debugger demonstration

YouTube

Shipped BuildKit for RISC-V64. Green CI, packages built. Users tried it: crash loop.

"No worker found" - missing runc, wrong ENTRYPOINT/CMD, hanging tests.

Lessons:
✓ Test integration, not just compilation
✓ Add timeouts everywhere
✓ Document WHY, not just WHAT

Visible success hiding more profound problems. Post-deployment debugging is the real work.

https://bit.ly/4oRyNhf

#BuildKit #RISCV64 #Docker #DevOps #Debugging #PostDeployment #LessonsLearned #OpenSource #devEco

BuildKit for RISC-V64: When Your Package Works But Your Container Doesn’t | Bruno Verachten

I shipped BuildKit for RISC-V64 two days ago. The workflows were green, packages built successfully, documentation looked thorough. Then users tried to actually use it. The container crash-looped immediately. "No worker found." Turns out "successful compilation" and "functional deployment" are very different things. The problems: - Missing runc binary meant OCI worker couldn't initialize (BuildKit needs at least one worker to run) - ENTRYPOINT/CMD split was wrong, so Docker Buildx was unable to pass runtime arguments - CI tests hung indefinitely when buildkitd tried to initialize workers without proper privileges - Cached GHCR credentials caused false "access denied" errors Three PRs later, the container works. But here's what I learned: - Testing individual components isn't enough. You need to test how components integrate with the systems that actually use them. It's not enough to verify the car starts; you need to verify it drives. - Always add timeouts. Even commands that "should never hang" will eventually hang. - Use your own packages consistently. Mixing Debian's runc 1.1.12 with our runc 1.3.0 builds created unnecessary version complexity. - Document the WHY, not just the WHAT. Explain when to use container images vs. APT packages. Users need context, not just instructions. The iceberg metaphor fits perfectly: visible success hiding more profound integration problems. Post-deployment debugging is where the real work happens. #BuildKit #RISCV64 #Docker #DevOps #Debugging #ContainerTechnology #LessonsLearned #PostDeployment #devEco

Something is coming...

Yes, it's 4 AM right now. I've been doing this since around 1 AM.

Trust me, once it gets good, I'll properly reveal it.

It does have something to do with the #RISCV hardware I ordered recently.

I'll get somewhere with this, I promise, alright?

It may take longer than the hardware arrival, but I'll get there in the end.

#RISC #RISCV64 #Technology

Armbian 25.11 release is coming

Armbian 25.11 code freeze begins November 20th. Maintainers should test boards, resolve critical issues, and join the coordination meeting on November 8th.

Armbian blog