We wrapped up this weekend by starting the first RISCV builds for #Trisquel 12.

There's still a long way to go before we have the complete repository in RISCV, but this is the beginning of that journey.

Thanks to @jas for their financial support, which we've finally been able to incorporate into the project!

Read you around! 👋
#GNU #FreeSoftware #riscv64

Cerramos este fin de semana comenzando con las primeras construcciones de RISCV para #Trisquel 12

Todavía un largo camino antes de tener el repositoro completo en RISCV pero este es el inicio de ese camino.

Gracias a @jas por su colaboración económica, que por fin logramos reflejarla en el proyecto!

Seguimos en contacto! 👋
#GNU #SoftwareLibre #riscv64

Episode 9 of Dark Blue Weekly released

https://darkblueproject.com/sites/news/dbw-e9.php

#darkblueproject #darkblueweekly #linux #gnome #gnome50 #fedoraasahiremix #asahilinux #almalinux #riscv64 #blender #opensource #freesoftware

The irony: the entire RISC-V base ISA (RV64GC) is beautifully RISC: simple opcodes, fixed 32-bit instructions (+ compressed), load/store architecture, no flags, no implicit state. Then RVV comes along and throws all those principles out the window: global implicit state, microcode-like behavior, variable semantics of the same instruction.

Because vsetvli changes the semantics of all subsequent V-instructions based on the current VLEN configuration. For a JIT compiler in an Emulator and for an Emulator in general, this means having to continuously track the vtype state and react to any changes, a fundamental contradiction to the principle of statically analyzable instructions. It feels like the RISC-V Foundation sacrificed the simplicity and elegance of the RISC principle to create a powerful but extremely complex "super-SIMD" that is difficult to efficiently map in a JIT. A more traditional SIMD extension with fixed vector widths and clearly defined instruction semantics would have been much more JIT-friendly. The upcoming P extension does go in that direction, but it is primarily targeted at embedded and low-power applications rather than high-performance computing.

#riscv #riscv64 #emulation #pasriscv #object_pascal #delphi #free_pascal

🤸 updated #docker images for #duckdb v1.4.3
- based on Alpine: https://hub.docker.com/r/codieplusplus/duckdb
- based on Debian: https://hub.docker.com/r/codieplusplus/duckdb-debian

all multi-arch for #amd64, #arm64, #riscv64

I have that page about Arm cpu cores and their features.

RISC-V cpus has insane amount of extensions. I wonder when someone will make similar page about their details.

https://gpages.juszkiewicz.com.pl/arm-socs-table/arm-cpu-cores.html

#riscv64 #riscv

« Milk-V Titan : Powered by a 2 GHz UR-DP1000 octa-core RISC-V CPU, the Titan mini-ITX motherboard supports up to 64GB DIMM memory and M.2 NVMe storage (PCIe Gen4 x4), and features a PCIe Gen4 x16 slot for a graphics card or other expansion, Gigabit Ethernet, four USB 3.0 ports, a BMC, and more. »

› https://www.cnx-software.com/2026/01/12/milk-v-titan-a-329-octa-core-64-bit-risc-v-mini-itx-motherboard-with-a-pcie-gen4-x16-slot/

#RISC #RISCV #RISCV64 #MiniITX #Motherboard #OpenSource

Happy new #BSD year?

Is there any BSD variant that will run on the Sipeed LicheePi Console?

See:
https://wiki.sipeed.com/hardware/en/lichee/th1520/lcon4a/lcon4a.html

I guess not, but what do I know?
Thanks in advance.

#runbsd #riscv64 #licheepiconsole

PasRISCV now has its own local CLI debugger alongside the GDB remote server. It supports breakpoints, single-stepping, register & memory inspection, and allows simultaneous local CLI and remote GDB sessions. A public debugger API enables future graphical debugger frontends.

https://youtu.be/yznijHMKj_0

#riscv64 #riscv #emulation #pascal #object_pascal #debugger