siviqManaged to get #visionfive 2 lite with #riscv cpu working with DSI LCD 4.3” on Debian Trixie.
Keldrim 
Yoooo peeps new demo for for #RISC_V dropt, as always demosceners show on how to its done:
Gerard Braad
Michael EngelOpenBSD supports the 64-core RISC-V Milk-V Pioneer board since version 7.6.
However, this is not mentioned on the riscv64 port page (https://www.openbsd.org/riscv64.html), there is no information on installing OpenBSD on the Pioneer in the INSTALL.riscv64 docs and there also seems to be no RISC-V-specific mailing list for OpenBSD.
Does anyone have more information on running OpenBSD on this specific piece of hardware?
#riscv Compiling #debian Trixie for Risc-V CPU board (VisionFive 2 lite) on debian host system. It takes good amount of resources, but eventually will get there. :) Hope it will work... first time?
selfhosting.couchsurfingBanana Pi BPI-RV2: The RISC-V Router Board That Actually Works (OpenWRT Setup Guide)
Platima Tinkers reviews a #RISCV router board which just got working support in #OpenWrt within the past couple weeks. 512MB DDR3, PoE, NVMe, optional WiFi.
Banana Pi BPI-RV2: The RISC-V Router Board That Actually Works (OpenWRT Setup Guide)
Interfacing LinuxBanana Pi is doing a SpacemiT K3 (RVA23) board as well. Neat!
#linux #sbc #riscv
https://interfacinglinux.com/community/sbchardware/jupiter-2-rva23-risc-v-from-milk-v/#post-1094
#linux #sbc #riscv
https://interfacinglinux.com/community/sbchardware/jupiter-2-rva23-risc-v-from-milk-v/#post-1094
cnx-software.com192 MHz WCH CH32V205 RISC-V MCU offers a 480 Mbps USB 2.0 interface
192 MHz WCH CH32V205 RISC-V MCU offers a 480 Mbps USB 2.0 interface
WCH CH32V205 is a 32-bit RISC-V MCU clocked at up to 192 MHz with 32KB SRAM, 256KB flash, and a USB 2.0 high-speed Host/device interface with a 480 Mbps PHY. The new microcontroller also features another USB 2.0 full speed (12 Mbps) Host/Device interface, a USB PD port, eighty GPIOs, a 16-channel 12-bit ADC, a 16-channel touchkey interface, and other interfaces such as CAN Bus, USART, I2C, SPI, and QSPI. WCH CH32V205 specifications: MCU core - QingKe 32-bit RISC-V3B core processor up to 192 MHz Memory & Storage 32KB SRAM 256KB Flash Flexible Static Memory Controller (FSMC) Peripherals USB 480Mbps high-speed USB 2.0 controller and PHY Full-speed USB 2.0 controller and PHY USB PD and Type-C controller and PHY 8x USARTs, 2x I2C, 2x SPI , 1x QuadSPI 1-wire (default)/ 2-wire serial debug interface 1x CAN 2.0B Up to 80x GPIO with 16 external interrupts Programmable Protocol I/O Controller (PIOC). Note:
Banana Pi Open Source HardwareBanana Pi BPI-SM10(K3-CoM260) and K3 Pico-ITX will public sale soon.which module are you like,free discuss on our forum
https://forum.banana-pi.org/t/banana-pi-bpi-sm10-k3-com260-and-k3-pico-itx-will-public-sale-soon-which-module-are-you-like/27177
#bananapi #riscv #spacemit #K3 #AI #SOC #raspberrypi
https://forum.banana-pi.org/t/banana-pi-bpi-sm10-k3-com260-and-k3-pico-itx-will-public-sale-soon-which-module-are-you-like/27177
#bananapi #riscv #spacemit #K3 #AI #SOC #raspberrypi
Linux 7.0 Release – Main changes, Arm, RISC-V, and MIPS architectures
Linux 7.0 Release – Main changes, Arm, RISC-V, and MIPS architectures
Linus Torvalds has just released Linux 7.0 on LKML: The last week of the release continued the same "lots of small fixes" trend, but it all really does seem pretty benign, so I've tagged the final 7.0 and pushed it out. I suspect it's a lot of AI tool use that will keep finding corner cases for us for a while, so this may be the "new normal" at least for a while. Only time will tell. Anyway, this last week was a little bit of everything: networking (core and drivers), arch fixes, tooling and selftests, and various random fixes all over the place. Let's keep testing, and obviously tomorrow the merge window for 7.1 opens. I already have four dozen pull requests pending - thank you to all the early people. Linus This follows the Linux 6.19 release about two months ago, which brought us PCIe link encryption and