YRabbitNov 2

Classic Wizardry on #sipeed #Tangprimer25k!

Just kidding.🀣

The frame is a background image, but the maze itself and the strange spherical creature are the work of the @WillFlux 's 2D accelerator!

I'm doing this out of pure interest to check the accuracy of #apicula and #nextpnr on the GW5 series of #gowin #fpga

YRabbitSep 7, 2025
Very interesting. In #TangPrimer25k, six PLLs of the same type are listed. But I could only find two right away, and the picture from the datasheet is, to put it mildly, BS (not only are there not six PLLs, but the OSC also changes its position😜 ).
Okay, let's compile and compare; eventually, I'll find all six.πŸ˜‰ #fpga
YRabbitAug 8, 2025

Gee! #apicula has learned to use the internal clock generator (well, not entirely internal, it is still external to the chip, but soldered permanently to the #TangPrimer25k board).😜

We are slowly but surely moving towards decent support for the GW5 series of #gowin #fpga!πŸ˜€

YRabbitJul 23, 2025

GW5 family (#TangPrimer25k) got support for huge LUTs in #apicula!🍾

#fpga#sipeed#gowin

YRabbitJul 18, 2025

Yes, definitely the IO bits (#Tangprimer25k) are not set in the IO cell itself, but in the neighboring column or neighboring row. As usual this is not always the case.🀣

Will look for.#fpga

YRabbitJul 16, 2025
It's about to rain outside, so let's see what's so mysterious about the #TangPrimer25k IO blocks. For some reason, the bits responsible for the B blocks do not appear where I expect them to appear. 🀣 #fpga