Icepi Zero Bot module my_code #(
parameter int WIDTH = 640,
parameter int HEIGHT = 480,
parameter int CONSOLE_COLUMNS = WIDTH / 8,
parameter int CONSOLE_ROWS = HEIGHT / 8
)(
input logic clk,
input logic rst,
input int px,
input int py,
input logic hsync,
input logic vsync,
input int col,
input int row,
output int char,
output logic [23:0] foreground_color,
output logic [23:0] background_color,
output logic [7:0] uart_data,
input logic uart_ready,
output logic uart_valid
);
// NO inline initializations to avoid TOK_CONSTVAL parser errors
logic [31:0] frame_counter;
logic old_vsync;
logic [6:0] msg_idx;
logic sending;
// Registers to lock the UART VU meter levels across a single frame
logic [4:0] l_samp;
logic [4:0] r_samp;
// Combinational logic variables
logic [7:0] x_mod1;
logic [7:0] x_mod2;
logic [4:0] tri1;
logic [4:0] tri2;
logic [5:0] total_h;
logic [5:0] dot_h;
logic [5:0] inv_row;
logic [7:0] u_mod1;
logic [7:0] u_mod2;
logic [4:0] u_tri1;
logic [4:0] u_tri2;
always_comb begin
// ---------------------------------------------------------
// 1. VIDEO: Hardware Spectrum Analyzer
// ---------------------------------------------------------
// Generate two counter-propagating waves of different speeds.
// Bitwise AND with 3F limits the wave period to 64 columns.
x_mod1 = (col[7:0] + frame_counter[7:0]) & 8'h3F;
x_mod2 = (col[7:0] - frame_counter[8:1]) & 8'h3F;
// Turn the ramping counters into absolute triangle waves (0 to 31)
tri1 = x_mod1[5] ? (~x_mod1[4:0]) : x_mod1[4:0];
tri2 = x_mod2[5] ? (~x_mod2[4:0]) : x_mod2[4:0];
// Sum the waves to get a morphing interference pattern (0 to 62 max height)
total_h = {1'b0, tri1} + {1'b0, tri2};
// Calculate the position of the floating "peak" dot
dot_h = total_h + 6'd2;
// Invert the row coordinate so row 0 is the bottom of the screen
inv_row = 6'd59 - row[5:0];
// Render the equalizer bars
if (col[0] == 1'b1) begin
// Leave a 1-character gap between every frequency band
char = 8'h20; // ' '
foreground_color = 24'd0;
background_color = 24'd0;
end else if (inv_row < total_h) begin
// Draw the main LED bar
char = 8'h3D; // '=' character gives it a segmented LED look
background_color = 24'd0;
// Heatmap color gradient based on height
if (inv_row < 6'd15)
foreground_color = 24'h00FF00; // Green
else if (inv_row < 6'd30)
foreground_color = 24'hFFFF00; // Yellow
else if (inv_row < 6'd45)
foreground_color = 24'hFF8000; // Orange
else
foreground_color = 24'hFF0000; // Red
end else if (inv_row == dot_h) begin
// Draw the floating peak indicator
char = 8'h2D; // '-'
foreground_color = 24'hFFFFFF; // White
background_color = 24'd0;
end else begin
// Empty space above the bar
char = 8'h20; // ' '
foreground_color = 24'd0;
background_color = 24'd0;
end
// ---------------------------------------------------------
// 2. UART: Stereo VU Meter Sampling
// ---------------------------------------------------------
// Sample the triangle waves at the center of the screen independently of the
// video generation logic, so the UART doesn't change mid-frame.
u_mod1 = (frame_counter[7:0]) & 8'h3F;
u_mod2 = (-frame_counter[8:1]) & 8'h3F;
u_tri1 = u_mod1[5] ? (~u_mod1[4:0]) : u_mod1[4:0];
u_tri2 = u_mod2[5] ? (~u_mod2[4:0]) : u_mod2[4:0];
// ---------------------------------------------------------
// 3. UART: ASCII Output FSM
// ---------------------------------------------------------
if (msg_idx == 7'd0) uart_data = 8'h5B; // '['
else if (msg_idx == 7'd1) uart_data = 8'h4C; // 'L'
else if (msg_idx == 7'd2) uart_data = 8'h5D; // ']'
else if (msg_idx == 7'd3) uart_data = 8'h20; // ' '
else if (msg_idx == 7'd4) uart_data = 8'h7C; // '|'
else if (msg_idx >= 7'd5 && msg_idx <= 7'd36) begin
// 32-character Left channel bar
if ((msg_idx - 7'd5) < {2'b00, l_samp})
uart_data = 8'h23; // '#'
else
uart_data = 8'h2D; // '-'
end
else if (msg_idx == 7'd37) uart_data = 8'h7C; // '|'
else if (msg_idx == 7'd38) uart_data = 8'h20; // ' '
else if (msg_idx == 7'd39) uart_data = 8'h5B; // '['
else if (msg_idx == 7'd40) uart_data = 8'h52; // 'R'
else if (msg_idx == 7'd41) uart_data = 8'h5D; // ']'
else if (msg_idx == 7'd42) uart_data = 8'h20; // ' '
else if (msg_idx == 7'd43) uart_data = 8'h7C; // '|'
else if (msg_idx >= 7'd44 && msg_idx <= 7'd75) begin
// 32-character Right channel bar
if ((msg_idx - 7'd44) < {2'b00, r_samp})
uart_data = 8'h23; // '#'
else
uart_data = 8'h2D; // '-'
end
else if (msg_idx == 7'd76) uart_data = 8'h7C; // '|'
else if (msg_idx == 7'd77) uart_data = 8'h0D; // '\r'
else if (msg_idx == 7'd78) uart_data = 8'h0A; // '\n'
else uart_data = 8'h20; // Space
end
// --- SEQUENTIAL LOGIC ---
always_ff @(posedge clk) begin
if (rst) begin
frame_counter <= 0;
old_vsync <= 0;
msg_idx <= 0;
uart_valid <= 1'b0;
sending <= 1'b0;
l_samp <= 0;
r_samp <= 0;
end else begin
// Track frames on the falling edge of vsync
if (vsync == 1'b0 && old_vsync == 1'b1) begin
frame_counter <= frame_counter + 1;
// Latch the VU meter samples so they stay stable during UART transmission
l_samp <= u_tri1;
r_samp <= u_tri2;
// Trigger one line of UART output per frame
sending <= 1'b1;
end
old_vsync <= vsync;
// UART Handshaking FSM
if (sending) begin
uart_valid <= 1'b1;
if (uart_ready && uart_valid) begin
if (msg_idx == 7'd79) begin
msg_idx <= 0;
uart_valid <= 1'b0;
sending <= 1'b0; // Wait for the next vsync frame
end else begin
msg_idx <= msg_idx + 1;
end
end
end else begin
uart_valid <= 1'b0;
end
end
end
endmodule
UtilizationCellUsedAvailableUsage
TimingClockAchievedConstraint
Code
#FPGA #Icepi-Zero #HDL #SystemVerilog
Success!
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UtilizationCellUsedAvailableUsage
DCCA2563.6%EHXPLLL1250.0%TRELLIS_COMB696242882.9%TRELLIS_FF150242880.6%TRELLIS_IO111975.6%TimingClockAchievedConstraint
$glbnet$clkp84.79 MHz25 MHz$glbnet$clkt335.68 MHz250 MHzCode
module my_code #(
parameter int WIDTH = 640,
parameter int HEIGHT = 480,
parameter int CONSOLE_COLUMNS = WIDTH / 8,
parameter int CONSOLE_ROWS = HEIGHT / 8
)(
input logic clk,
input logic rst,
input int px,
input int py,
input logic hsync,
input logic vsync,
input int col,
input int row,
output int char,
output logic [23:0] foreground_color,
output logic [23:0] background_color,
output logic [7:0] uart_data,
input logic uart_ready,
output logic uart_valid
);
// NO inline initializations to avoid TOK_CONSTVAL parser errors
logic [31:0] frame_counter;
logic old_vsync;
logic [6:0] msg_idx;
logic sending;
// Registers to lock the UART VU meter levels across a single frame
logic [4:0] l_samp;
logic [4:0] r_samp;
// Combinational logic variables
logic [7:0] x_mod1;
logic [7:0] x_mod2;
logic [4:0] tri1;
logic [4:0] tri2;
logic [5:0] total_h;
logic [5:0] dot_h;
logic [5:0] inv_row;
logic [7:0] u_mod1;
logic [7:0] u_mod2;
logic [4:0] u_tri1;
logic [4:0] u_tri2;
always_comb begin
// ---------------------------------------------------------
// 1. VIDEO: Hardware Spectrum Analyzer
// ---------------------------------------------------------
// Generate two counter-propagating waves of different speeds.
// Bitwise AND with 3F limits the wave period to 64 columns.
x_mod1 = (col[7:0] + frame_counter[7:0]) & 8'h3F;
x_mod2 = (col[7:0] - frame_counter[8:1]) & 8'h3F;
// Turn the ramping counters into absolute triangle waves (0 to 31)
tri1 = x_mod1[5] ? (~x_mod1[4:0]) : x_mod1[4:0];
tri2 = x_mod2[5] ? (~x_mod2[4:0]) : x_mod2[4:0];
// Sum the waves to get a morphing interference pattern (0 to 62 max height)
total_h = {1'b0, tri1} + {1'b0, tri2};
// Calculate the position of the floating "peak" dot
dot_h = total_h + 6'd2;
// Invert the row coordinate so row 0 is the bottom of the screen
inv_row = 6'd59 - row[5:0];
// Render the equalizer bars
if (col[0] == 1'b1) begin
// Leave a 1-character gap between every frequency band
char = 8'h20; // ' '
foreground_color = 24'd0;
background_color = 24'd0;
end else if (inv_row < total_h) begin
// Draw the main LED bar
char = 8'h3D; // '=' character gives it a segmented LED look
background_color = 24'd0;
// Heatmap color gradient based on height
if (inv_row < 6'd15)
foreground_color = 24'h00FF00; // Green
else if (inv_row < 6'd30)
foreground_color = 24'hFFFF00; // Yellow
else if (inv_row < 6'd45)
foreground_color = 24'hFF8000; // Orange
else
foreground_color = 24'hFF0000; // Red
end else if (inv_row == dot_h) begin
// Draw the floating peak indicator
char = 8'h2D; // '-'
foreground_color = 24'hFFFFFF; // White
background_color = 24'd0;
end else begin
// Empty space above the bar
char = 8'h20; // ' '
foreground_color = 24'd0;
background_color = 24'd0;
end
// ---------------------------------------------------------
// 2. UART: Stereo VU Meter Sampling
// ---------------------------------------------------------
// Sample the triangle waves at the center of the screen independently of the
// video generation logic, so the UART doesn't change mid-frame.
u_mod1 = (frame_counter[7:0]) & 8'h3F;
u_mod2 = (-frame_counter[8:1]) & 8'h3F;
u_tri1 = u_mod1[5] ? (~u_mod1[4:0]) : u_mod1[4:0];
u_tri2 = u_mod2[5] ? (~u_mod2[4:0]) : u_mod2[4:0];
// ---------------------------------------------------------
// 3. UART: ASCII Output FSM
// ---------------------------------------------------------
if (msg_idx == 7'd0) uart_data = 8'h5B; // '['
else if (msg_idx == 7'd1) uart_data = 8'h4C; // 'L'
else if (msg_idx == 7'd2) uart_data = 8'h5D; // ']'
else if (msg_idx == 7'd3) uart_data = 8'h20; // ' '
else if (msg_idx == 7'd4) uart_data = 8'h7C; // '|'
else if (msg_idx >= 7'd5 && msg_idx <= 7'd36) begin
// 32-character Left channel bar
if ((msg_idx - 7'd5) < {2'b00, l_samp})
uart_data = 8'h23; // '#'
else
uart_data = 8'h2D; // '-'
end
else if (msg_idx == 7'd37) uart_data = 8'h7C; // '|'
else if (msg_idx == 7'd38) uart_data = 8'h20; // ' '
else if (msg_idx == 7'd39) uart_data = 8'h5B; // '['
else if (msg_idx == 7'd40) uart_data = 8'h52; // 'R'
else if (msg_idx == 7'd41) uart_data = 8'h5D; // ']'
else if (msg_idx == 7'd42) uart_data = 8'h20; // ' '
else if (msg_idx == 7'd43) uart_data = 8'h7C; // '|'
else if (msg_idx >= 7'd44 && msg_idx <= 7'd75) begin
// 32-character Right channel bar
if ((msg_idx - 7'd44) < {2'b00, r_samp})
uart_data = 8'h23; // '#'
else
uart_data = 8'h2D; // '-'
end
else if (msg_idx == 7'd76) uart_data = 8'h7C; // '|'
else if (msg_idx == 7'd77) uart_data = 8'h0D; // '\r'
else if (msg_idx == 7'd78) uart_data = 8'h0A; // '\n'
else uart_data = 8'h20; // Space
end
// --- SEQUENTIAL LOGIC ---
always_ff @(posedge clk) begin
if (rst) begin
frame_counter <= 0;
old_vsync <= 0;
msg_idx <= 0;
uart_valid <= 1'b0;
sending <= 1'b0;
l_samp <= 0;
r_samp <= 0;
end else begin
// Track frames on the falling edge of vsync
if (vsync == 1'b0 && old_vsync == 1'b1) begin
frame_counter <= frame_counter + 1;
// Latch the VU meter samples so they stay stable during UART transmission
l_samp <= u_tri1;
r_samp <= u_tri2;
// Trigger one line of UART output per frame
sending <= 1'b1;
end
old_vsync <= vsync;
// UART Handshaking FSM
if (sending) begin
uart_valid <= 1'b1;
if (uart_ready && uart_valid) begin
if (msg_idx == 7'd79) begin
msg_idx <= 0;
uart_valid <= 1'b0;
sending <= 1'b0; // Wait for the next vsync frame
end else begin
msg_idx <= msg_idx + 1;
end
end
end else begin
uart_valid <= 1'b0;
end
end
end
endmodule
#FPGA #Icepi-Zero #HDL #SystemVerilog
JCM
Jakub Cabal
Habr 25+
Habr
