Mastodawn

WASM is not quite a stack machine

https://purplesyringa.moe/blog/wasm-is-not-quite-a-stack-machine/

#HackerNews #WASM #stackmachine #programming #webassembly #techblog

Wasm is not quite a stack machine

Everyone knows Wasm is a stack machine. Wikipedia says so, the official Wasm design specification says so, you get it. I thought so too. That is, until I started writing Wasm code – not compiling for Wasm, but writing the instructions by hand. And I found out that there exists a major difference between Wasm and all other stack-based languages, that makes this claim misleading.

purplesyringa's blog

Open Source Electronics Wiki Feb 27

The best FPGA for Forth Soft Cross

Here is the abstract for my SVFIG talk at abpit 10:20 am California time tomorrow Saturday Feb 28th.

The $15 GateMate is a great FPGA for building Forth soft cores. It will happily run at 100Mhz or more. It has 64 x 1 K word long x 20 bit wide block RAMs (BRAMs). 20 bits wide is enough for most real time control applications.
Continued below ...
#Forth #StackMachine #ManyCore
https://www.meetup.com/sv-fig/events/313321014/?slug=sv-fig&eventId=313321014

February SVFIG ZOOM Meeting --- Fourth Saturday!, Sat, Feb 28, 2026, 9:30 AM | Meetup

**February Zoom Meeting!** ===== go to: **[forth.org/zoom](http://forth.org/zoom)** **for the SVFIG Zoom Meeting** **=====** **Fourth Saturday of February, 2026.** **=====*

Meetup

Show thread

Ramin Honary Feb 16

@jhlagado try “following” these hash tags:

It will probably improve the content of your stream slightly.

Open Source Electronics Wiki Nov 15, 2024

My new #Introduction

I am building tiny real-time #Forth co-processors for MicroPython, Circuit Python and RISC-V. On FPGA's a stack machine can be 1/2 the size of a 32 bit RISC-V soft core.

#Forth, #MicroPython #CircuitPython #Riscv #StackMachine #FPGA #Verilog
#realtime

PipelineC May 27, 2024

@tsalvo Just saw your work in progress on the stack #CPU implementation in #PipelineC 👋 . Great work, how neat! Hope it has gone well and as always happy to help! 🤓 #uxn #varvara #AnaloguePocket #FPGA #stackmachine #FPGA #HDL https://github.com/tsalvo/varvara-fpga

GitHub - tsalvo/varvara-fpga: implementation of Varvara / Uxn in FPGA

implementation of Varvara / Uxn in FPGA. Contribute to tsalvo/varvara-fpga development by creating an account on GitHub.

GitHub

Open Source Electronics Wiki Mar 29, 2024

I have created a Read The Docs site for Mecrisp Ice, which is a family of 16, 32 and 64 bit soft core Forth processors written in Verilog and based on the J1 stack machine.

https://mecrisp-ice.readthedocs.io

@Mecrisp #mecrisp #fpga #forth #j1 #stackmachine #readthedocs