I've got I/O needs... Like 35 GPIO lines and 8 devices on an 8Mhz SPI bus level of needs. A big I/O processor demultiplexed down to a UART; not a lot of CPU, just a lot of realtime shuttling of small packets of data....

#Adalang on an #ATMega2560 or #Forth ( #Mecrisp-ice on a Lattice #FPGA )?

Choices...

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

mecrisp-ice on my iCEBreaker FPGA board. So cool. The first time synthesizing my own Forth CPU.

Thanks to Matthias for the Mecrisp project.
@Mecrisp

#forth #mecrisp #fpga #icebreaker

Hana-1: Programmable I/O for FPGAs

Here is what I am building.

https://forth.pythonlinks.info/

#FPGA #Forth #Mecrisp #MecrispIce