The best FPGA for Forth Soft Cross

Here is the abstract for my SVFIG talk at abpit 10:20 am California time tomorrow Saturday Feb 28th.

The $15 GateMate is a great FPGA for building Forth soft cores. It will happily run at 100Mhz or more. It has 64 x 1 K word long x 20 bit wide block RAMs (BRAMs). 20 bits wide is enough for most real time control applications.
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#Forth #StackMachine #ManyCore
https://www.meetup.com/sv-fig/events/313321014/?slug=sv-fig&eventId=313321014

February SVFIG ZOOM Meeting --- Fourth Saturday!, Sat, Feb 28, 2026, 9:30 AM | Meetup

**February Zoom Meeting!** ===== go to: **[forth.org/zoom](http://forth.org/zoom)** **for the SVFIG Zoom Meeting** **=====** **Fourth Saturday of February, 2026.** **=====*

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The memories can be joined with hard core connections, so a J1 can be a lot smaller and thus faster on this device than on the original ICE 40 devices. There are enough resources to build six J1s on a ring network with room to spare. If you build a J4 barrel processor, then you can have 24 soft cores.Or you can buy a single GateMate chip with 25 GateMate FPGA interconnected cores and have 600 Forth Soft cores on a single die.
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The Mecrisp Ice Forth interpreter requires about 5K of RAM, a customasm application requires less. If you replace Forth with #customasm, then you could give a stack machine 1K words of memory and 1K words of program , which would give you 64 cores on a single GateMate, or 1600 soft core stack machines on the largest. GateMate chip. And you can connect them in whatever topology you want.
---All that we need is an application.---