Start rtl counter with a timer that is initialized 10 seconds from a 32bit wrap point so that the software handling of wrap-around is well exercised during development.

#rtl #fpga #verilog #vhdl #xilinx #alchitry #eureka #protonpack #software #softwaredevelopment #hardware #embedded #fensterFreitag

I plugged it in to USB... it powered on.
I went to plug in the second USB and as the metal made contact it suddenly powered off...

I saw no magic smoke.

It sure looks dead. I hope it's not a design flaw... because I just ordered two replacements.

#FPGA #Alchitry #Xilinx

https://forum.alchitry.com/t/regulator-failure-on-1v8-from-adp5052acpz-r7-on-pt-board/3546

#Alchitry Pt #FPGA board has a Br Break out board. It's all differentially routed. But wow, not an exemplar break-out for 6+GHz capable pairs. Even if it were for 10MHz signals, that breakout pattern is terrible. Swiss cheeze.

I guess for only fifteen bucks it's good enough, but yeah, maybe for the next spin you could hook up more than one ground pin? At least the pinout on the FPGA board seems to have a good number of ground pins.

But now I should inspect the Pt layout closely.

More in alt.

YAY, #neorv32 built with a VERY simple memory interface which I've connected to LEDs on my #Alchitry #FPGA board
I can now send data via memory to my own custom blocks (I think).

Next step is to figure out the memory mapping proper.

#Retroputer #FPGA Update

Bought a 2.4" TFT ILI9341 from @adafruit and connected it up via 4-line SPI using #Alchitry Br (breakout board). I added an I/O device so the CPU can send D/C select bits and data bytes using a FIFO buffer.

After a bit of a false start (involved adapting Adafruit's init sequence and experimentation), we have something coherent on the screen!

Super slow to fill the screen w/ #BASIC (using OUT commands), but validates that my understanding mostly matches reality. Woot!