YAY, #neorv32 built with a VERY simple memory interface which I've connected to LEDs on my #Alchitry #FPGA board
I can now send data via memory to my own custom blocks (I think).

Next step is to figure out the memory mapping proper.

Doing some cleanups for next year's courses ...

Just want to say I love using #neorv32 on the #de0nano ... such a good teaching platform !

https://github.com/stnolting/neorv32

#riscv

Geilo, after days of trying to figure out how it works, I finally got a Xilinx axi_uart16550 behind a PCI Express endpoint to work as a practically auto-detected tty on Linux, modifying the 8250_pci driver.

So, now there’s /dev/ttyS4 directly talking to a #neorv32 softcore #riscv MCU on an #FPGA.

Now, to clean-up and understanding what I’ve actually done.

#linux #kernel #module #driver #tinkering

Oh, wow, I am pleased af. I started looking into #neorv32, an #foss RISC-V soft-core MCU (i.e. it’s written in VHDL and can be synthesized onto an FPGA) is working smooth and nicely.
This is so much better an experience than what I’ve had so far with commercial stuff (yes, looking at you Xilinx)!

You go through the docs, find everything, get everything explained with no superfluous BS. The examples work right away. The docs even explain how to set up the gcc toolchain for riscv32 (Ubuntu seems to only come with a riscv64 toolchain).

And there you go: One 100 line VHDL top file (out of which only 22 lines are devoted to the neorv32 soc), some serial terminal (don’t use minicom, just don’t) and one 30 line C example later, I’ve got the blinks! (Bare in mind: I’m absolutely not an embedded dev!)

https://github.com/stnolting/neorv32

Custom RISC-V Processor Built in VHDL

While ARM continues to make inroads into the personal computing market against traditional chip makers like Intel and AMD, it's not a perfect architecture and does have some disadvantages. While it's a great step on the road to software and hardware freedom, it's not completely free as it requires a license to build. There is one completely open-source and free architecture though, known as RISC-V, and its design and philosophy allow anyone to build and experiment with it, like this build which implements a RISC-V processor in VHDL.

Since the processor is built in VHDL, a language which allows the design and simulation of integrated circuits, it is possible to download the code for the processor and then program it into virtually any FPGA. The processor itself, called NEORV32, is designed as a system-on-chip complete with GPIO capabilities and of course the full RISC-V processor implementation. The project's creator, [Stephan], also struggled when first learning about RISC-V so he went to great lengths to make sure that this project is fully documented, easy to set up, and that it would work out-of-the-box.

Of course, since it's completely open-source and requires no pesky licensing agreements like an ARM platform might, it is capable of being easily modified or augmented in any way that one might need. All of the code and documentation is available on the project's GitHub page. This is the real benefit of fully open-source hardware (or software) which we can all get behind, even if there are still limited options available for RISC-V personal computers for the time being.

How does this compare to VexRISC or PicoSOC? We don't know yet, but we're always psyched to have choices.

#fpga #softwarehacks #hardware #neorv32 #opensource #riscv #soc #vhdl