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@[email protected] asked
#[no_mangle(all)]
entity my_code(
clk: clock,
rst: bool,
px: int<32>,
py: int<32>,
hsync: bool,
vsync: bool,
col: int<32>,
row: int<32>,
char: inv &int<32>,
foreground_color: inv &uint<24>,
background_color: inv &uint<24>,
) {
set char = &0;
set foreground_color = &0xFFFFFFu24;
set background_color = &0xFF7AFFu24;
}
Success!
UART Output
UtilizationCellUsedAvailableUsage
DCCA2563.6%
EHXPLLL1250.0%
TRELLIS_COMB359242881.5%
TRELLIS_FF113242880.5%
TRELLIS_IO101975.1%
TimingClockAchievedConstraint
$glbnet$clkp140.29 MHz25 MHz
$glbnet$clkt363.5 MHz250 MHz
Code
#[no_mangle(all)]
entity my_code(
clk: clock,
rst: bool,
px: int<32>,
py: int<32>,
hsync: bool,
vsync: bool,
col: int<32>,
row: int<32>,
char: inv &int<32>,
foreground_color: inv &uint<24>,
background_color: inv &uint<24>,
) {
set char = &0;
set foreground_color = &0xFFFFFFu24;
set background_color = &0xFF7AFFu24;
}
#FPGA #Icepi-Zero #HDL #Spade