I’ve had so much fun with the 486 SX-33 lately that I haven’t even touched the Switch 2 I got over the weekend.

I’m putting together a devkit for the MiSTeR FPGA ao486 core, and more generally an environment for retro game and demo-style projects. Toolchains in this space have been fairly grim so far: DJGPP, Turbo C++, or Watcom C/C++.

• GCC and LLVM support. COM output is supported through a linker script, and EXE output is supported as well. A Lua script prepends an MZ header to the EXE.
• A chain loader switches to protected mode and loads the program into extended memory.
• Rather than relying on DOSBox or 86Box, I tuned QEMU very carefully. It now feels surprisingly close to the ao486 core in practice.
• If this were a 386 SX devkit, I would probably have gone with flat real mode or so-called “unreal mode”. On a 486, though, the 0x66 and 0x67 prefixes used for 32-bit instructions already eat into performance on what is still a fairly modest CPU. The pipeline is only 16 bytes long.
• There is a small proof of concept included, but only the bare minimum. I’m saving the more interesting material for my own retro projects. The idea is to provide a blank canvas built on a much better SDK.
• 486.md covers 486-specific assembly optimisation details. In practice, it is quite a different beast from either a 386 or a Pentium. This is the sort of material that is fun to read on its own, so it felt worth writing.
• The package includes the Unscii font, apparently pulled from GitHub, though I can no longer find the exact source URL. The original project is here: http://viznut.fi/gfx/fonts/
• It also includes tmodplay, a MOD player. Unfortunately, the Sound Blaster 16 implementation in ao486 is pretty awful. For that era of PC hardware, the only really good option was the Gravis Ultrasound.
• The target configuration has 16 MiB of RAM. That would have been an unusual combination back in the day, but those are the ao486 defaults, so I’m leaning into a kind of retro-modern setup. The other default was some completely absurd number.
• There is also a proof-of-concept demo with a four-layer parallax scroller and various informational texts.

I’m not really a game or demo developer myself, but I can at least provide much better SDKs, so I felt like fixing one long-standing problem in the retro scene. It is released under the MIT license so people can do whatever they like with it.

I should also check whether that FPGA core supports VESA 2.0, because that would allow 320x240 with chunky pixels. VESA 1.x was awful.

#Intel #486 #ao486 #MiSTeR #FPGA

scp images/linux/BOOT.BIN [email protected]:

dann als root@fpga

xmutil bootfw_status
xmutil bootfw_update -i /home/petalinux/BOOT.BIN
reboot

wenn boot tut gut:
xmutil bootfw_update -v

#FPGA #BOOTBIN #FirmwareUpdate #soGehtDas

Ohhhh free candy with my #fpga board.

#electronics

Ternary CPU on FPGA breaks 60-year hardware drought

#TernaryComputing #FPGA #HardwareNews #AusNews #AIGenerated

https://thedailyperspective.org/article/2026-03-18-ternary-cpu-on-fpga-breaks-60-year-hardware-drought-4a52d3a9

Our workshop Languages and Tools for Accelerator Design is next week on March 23. We finally published the schedule over at https://capra.cs.cornell.edu/latte26/, and all the papers are online if you want to start reading already!

Attend on Zoom or in person if you're at ASPLOS this year!

#fpga #asic

High-end 25MP global shutter camera with 10GbE interface is designed for NVIDIA Holoscan platform

https://fed.brid.gy/r/https://www.cnx-software.com/2026/03/18/high-end-25mp-global-shutter-camera-with-10gbe-interface-is-designed-for-nvidia-holoscan-platform/

POSSE is done. Work is peaking. But I have a Xilinx VC707 and a pre-production Skylake-X box collecting dust, and an FPGA side project taking shape in my head (399 words)
#fpga #verilator #hardwaredev #sideproject #posse

🔗 https://behindtheviewfinder.com/side-project-fpga/

Выступил отрицателем AI на конференции SNUG Silicon Valley

AI - не микроархитектор, не проектировщик и не верификатор. Это все-лишь гламурный поисковик уже решенных и опубликованных задач. Именно такой вывод следовал из предоставленных мною на конференции SNUG Silicon Valley 2026 фактов как десятки студентов мучали ИИ чтобы решить мои задачки. Одну задачку ИИ решил лишь через полгода после выкладывания решений в интернет, другую за два месяца, потом пошла третья. При этом задачки были довольно банальные - мы в Самсунге даем делать такие статические конвейеры с контролем потока данных практикантам. Вот постер, сопровождающий мою статью:

https://habr.com/ru/articles/1010978/?utm_source=habrahabr&utm_medium=rss&utm_campaign=1010978

#SNUG #Synopsys #Silicon_Valley #школа_синтеза_цифровых_схем #SystemVerilog #ASIC #FPGA #Samsung #задачи_на_собеседованиях #VHDL