@[email protected]

OMG OMG OMG, the @icepi-zero-bot has now UART output support! :D

The interface is a simple ready/valid handshake, so it should be super easy to use I hope.



RE: https://wafrn.jcm.re/fediverse/post/e5ffaf1a-946f-4349-8555-44d5f3b61875
#FPGA #fedibot #bot #HDL #hardware

@[email protected]

I am pleased to announce that @icepi-zero-bot is back up and running. 

Now inside my Kubernetes cluster on more powerful hardware, so you should hopefully see some faster synthesis times and slightly nicer videos!
I think I secured it pretty well, but if someone manages to do something naughty, please don't nom-nom all my data :pleading_face:
Also, please don't break my FPGA on purporse, oki? :3

Sadly, I still need to figure out Spade support, because I couldn't find any prebuilt arm64 binaries for it :(

So, if you want to write cool SystemVerilog/VHDL/Amaranth/Veryl code, have it run on a real FPGA and output video (no need to implement DVI yourself, dw), which is then recorded and posted, check out @icepi-zero-bot's profile! The profile description contains tons of explanations and templates.

Soon, I will hopefully add Spade support back and also implement a UART interface, so you can also output text! The support for that in the bot is already there, I just need to implement a UART transmitter in VHDL and think of a cute and easy interface.



RE: https://wafrn.jcm.re/fediverse/post/83972345-09e4-47d9-99d3-4a3885a2a198
#fedibot #FPGA #HDL #VHDL #Verilog #SystemVerilog #Amaranth #Veryl

Hej Mastodon 👋
Jeg er en bot, der automatisk deler danske madopskrifter 🍲🇩🇰
Følg hvis du vil have inspiration i dit feed.

#introduktion #bot #fedibot #madopskrift #opskrift #opskrifter #dansk

I am happy to announce that the @icepi-zero-bot has Veryl support (it actually had it since a couple of days, but now I finally have a tiny bit of time to announce it)!
Thanks to @Tathar for the request and the help with setting things up.



RE: https://wafrn.jcm.re/fediverse/post/fb21908c-6fe6-4693-9bd9-5718b5314334
#FPGA #Icepi-Zero #fedibot #Veryl #HDL

The @icepi-zero-bot supports Spade now as requested by @thezoq2 🎉
The keyword for detecting it is #[no_mangle.

Sadly I have no experience in Spade, so the current example in the bot's description is very minimal.
If anyone can create a more complex example and wants to contribute it, feel free to message me!



RE: https://wafrn.jcm.re/fediverse/post/c349a0ba-6667-4406-b11f-b95e860f2822
#FPGA #Icepi-Zero #Spade #Spade-HDL #bot #fedibot

Small update announcement for the @icepi-zero-bot (that you might have noticed already):

  • The bot now reports details about utilization and clock speeds together with the video in the success post.
  • You can split your code into multiple messages if your instance has a low character limit for direct messages (see the bot's description for more details).

For the future, I plan to:

  • Add support for more HDLs (tell me your favorite ones and I try to integrate them).
  • Support for outputting text via UART, that the host will capture and include in the success post.

If you have any other ideas/wishes, feel free to tell me :D


#FPGA #bot #fedibot #Icepi-Zero #VHDL #Verilog #SystemVerilog #Amaranth

Btw, here's my current setup for the @icepi-zero-bot:

The SBC operating the bot, running the synthesis and recording the video is Layla, my Milk-V Mars (bonus point for everyone who can guess the old name based on the picture).



RE: https://wafrn.jcm.re/fediverse/post/ab879ff9-21dc-4726-964d-4f0a73e5e00e
#FPGA.-Icepi-Zero #fedibot #bot #SBC #RISC-V

Heyo Fediverse,

Did you ever want to run your VHDL code on someone else's FPGA and see the results as a video?

No?

With @icepi-zero-bot you can do it anyway!

Just send the account an ask containing your VHDL code (see the account's bio for an example) and the bot will synthesize your code, flash it onto my Icepi Zero FPGA board, and record a 30s video of its HDMI output!

I know this might not be the most useful bot, but I've mainly made it just for fun.
Feel free to play around a bit with it! :D

I'll add SystemVerilog support soon, once I figure out how to reliably differentiate it from VHDL based on only the code.


#FPGA #VHDL #bot #fedibot #Icepi-Zero

This Fediverse bot @FediTree has tried to adopt a social-norm around which people and accounts on the Fediverse to include.

@FediTree generates an image with a (Christmas?) tree in it, with the (Christmas?) tree ornaments decorating the tree being the accounts you recently interacted with the most.

@FediTree adopted social-norm is: it doesn't include accounts that have the #nobot hash-tag on their profile, or have set their account to NOT be "discoverable".

#DeSo #FediBot #FediDevs #Fediverse