#CVUTFEL ( #CVUT FEE) Advanced Computer Architecture ( #comparch) course recodings of the first five lectures are published at #VHSky.cz. Czech language recordings from the 2021 round are available as well. The B4M35PAP course builds on the knowledge from the introductory #comparch B35APO course (recordings). Each student builds their own CPU design (tools and ISA are open). The #QtRvSim #RISCV educational simulator is provided for inspiration (online version and The Czech Technical University #comparch related courses guidepost https://comparch.edu.cvut.cz/).

P.S.: Help with tooling for transcribing the lectures in my Czenglish dialect into English subtitles would be appreciated, as well as all other forms of feedback. For the introductory course, we provide reusable LaTeX sources (CC-BY-SA license) that are open to pull requests.

Summer 2025 #cvut defended theses by OTREES / “my” students:

• Matyáš Bobek, FlexCAN Controller Emulation for QEMU, #qemu #canbus (git), I hope for mainlining soon, my thanks to
  @marckleinebudde for review
• Albert Bezděk, Stereo Camera FPGA Interface and Processing for Zynq Based Systems, with initial rectification and disparity in #XilinX #Zynq #FPGA (git), thank to Martin Meloun for review
• Michal Matiáš, NuttX RTOS Driver for Single Unshielded Twisted Pair Communication, working with ncv7410 and ESP32-C6 for now (nuttx, apps git), continues by #GSoC expected to lead to broader OpenAlliance SPI Ethernet MAC-PHY T1S for mainline #NuttX support after summer, thanks to @cynerd for review

See the last OTREES theses list for link to repositories and more

Another related theses from #cvut Faculty of Information Technologies mentored by Michal Štepanovský to mention:

• Jan Medek, Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support, port (git) of #NuttX to the own setup of Ibex #riscv to Digilent Basys 3 and Digilent Nexys Video, includes even #NuttX, #RTEMS, #Zephyr, #FreeRTOS and RT-Thread choice analysis, some minor clarifications in my review, out of the text documentation, the student ported NuttX even to the CPU system prepared in frame of the next thesis
• Ondřej Golasowski, RISC-V open-source microarchitecture analysis and optimization, the VESP-BETA single-cycle RV32IMZicsr #riscv design for basic #comparch education with #FPGA labs

Stay tuned next summer as well, there is student interested in thesis to add MMU to #QtRvSim