Pavel PisaPavel Píša: Advanced Computer Architectures – 08 Memory Consistency [M35PAP Winter 25/26]
PeerTube
Pavel Píša: Advanced Computer Architectures – 09 Parallel Execution [M35PAP Winter 25/26]
Pavel Píša: Advanced Computer Architectures – 09 Parallel Execution [M35PAP Winter 25/26]
Pavel Píša: Advanced Computer Architectures – 06 Memory Subsystem [M35PAP Winter 25/26]
Pavel Píša: Advanced Computer Architectures – 06 Memory Subsystem [M35PAP Winter 25/26]
Pavel Pisa#CVUTFEL ( #CVUT FEE) Advanced Computer Architecture ( #comparch) course recodings of the first five lectures are published at #VHSky.cz. Czech language recordings from the 2021 round are available as well. The B4M35PAP course builds on the knowledge from the introductory #comparch B35APO course (recordings). Each student builds their own CPU design (tools and ISA are open). The #QtRvSim #RISCV educational simulator is provided for inspiration (online version and The Czech Technical University #comparch related courses guidepost https://comparch.edu.cvut.cz/).
P.S.: Help with tooling for transcribing the lectures in my Czenglish dialect into English subtitles would be appreciated, as well as all other forms of feedback. For the introductory course, we provide reusable LaTeX sources (CC-BY-SA license) that are open to pull requests.
Summer 2025 #cvut defended theses by OTREES / “my” students:
- Matyáš Bobek, FlexCAN Controller Emulation for QEMU, #qemu #canbus (git), I hope for mainlining soon, my thanks to
@marckleinebudde for review - Albert Bezděk, Stereo Camera FPGA Interface and Processing for Zynq Based Systems, with initial rectification and disparity in #XilinX #Zynq #FPGA (git), thank to Martin Meloun for review
- Michal Matiáš, NuttX RTOS Driver for Single Unshielded Twisted Pair Communication, working with ncv7410 and ESP32-C6 for now (nuttx, apps git), continues by #GSoC expected to lead to broader OpenAlliance SPI Ethernet MAC-PHY T1S for mainline #NuttX support after summer, thanks to @cynerd for review
See the last OTREES theses list for link to repositories and more
Another related theses from #cvut Faculty of Information Technologies mentored by Michal Štepanovský to mention:
- Jan Medek, Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support, port (git) of #NuttX to the own setup of Ibex #riscv to Digilent Basys 3 and Digilent Nexys Video, includes even #NuttX, #RTEMS, #Zephyr, #FreeRTOS and RT-Thread choice analysis, some minor clarifications in my review, out of the text documentation, the student ported NuttX even to the CPU system prepared in frame of the next thesis
- Ondřej Golasowski, RISC-V open-source microarchitecture analysis and optimization, the VESP-BETA single-cycle RV32IMZicsr #riscv design for basic #comparch education with #FPGA labs
Stay tuned next summer as well, there is student interested in thesis to add MMU to #QtRvSim
@frankenswine @LainTrain If you want to start learning #riscv ISA then the basic introduction to the minimal set of RV32 instructions can be found at our #comparch course tutorial page https://cw.fel.cvut.cz/wiki/courses/b35apo/en/tutorials/03/start .
You can test the code on the #QtRvSim single-cycle simulator setup and then follow to the pipelined version. The simulator can be installed on GNU/Linux, Windows, MAC OS and online version is available at https://comparch.edu.cvut.cz/ . The related lectures are available at https://cw.fel.cvut.cz/wiki/courses/b35apo/en/lectures/start . There are even advertisements free accessible recordings available at https://vhsky.cz/w/p/8Ejstt3Tfh8mWGcjQcEL2S
You can test the code on the #QtRvSim single-cycle simulator setup and then follow to the pipelined version. The simulator can be installed on GNU/Linux, Windows, MAC OS and online version is available at https://comparch.edu.cvut.cz/ . The related lectures are available at https://cw.fel.cvut.cz/wiki/courses/b35apo/en/lectures/start . There are even advertisements free accessible recordings available at https://vhsky.cz/w/p/8Ejstt3Tfh8mWGcjQcEL2S
The new book how to build #riscv processor for #comparch courses is on the horizon (ETA later H2 2025) RISC-V System-on-Chip Design by D. Harris, J. Stine, R. Thompson, S. Harris. It has been presented at the RISC-V International Academic and Training SIG meeting. The recording of the session is available on YouTube https://youtu.be/Qyq5nHUDt4g The related configurable RV32I to RV64IMAFDCB core and Wally SoC sources https://github.com/openhwgroup/cvw
If you want to learn #RiscV basic principles yourself or use it in your computer architectures #comparch basic classes, then you can use our really open and fully shared resources, no registration required for experimenting online https://comparch.edu.cvut.cz/, downloading #QtRvSim packages for all major desktop operating systems #linux, #macos, #mswidows and obtaining lectures with the sources https://cw.fel.cvut.cz/wiki/courses/b35apo/en/lectures/start and recordings on YouTube and even advertisement-free community PeerTube instance VHSky.cz. We offer even online training and and competition site https://comparch.edu.cvut.cz/online-tools/webeval/. In this case, we store SHA1 of your e-mail only for purpose to allow participants to reset their password. So again we do not intend and even cannot use your registration for advertisement for paid courses etc.
bgergelyexample: ordering of memory writes.
on a strongly ordered system, writes are reordered to program order before commiting (actually writing to D$). On a weakly ordered memory system, writes to different locations can happen in different order #uarch #comparch #microarchitecture
on a strongly ordered system, writes are reordered to program order before commiting (actually writing to D$). On a weakly ordered memory system, writes to different locations can happen in different order #uarch #comparch #microarchitecture
RSNikhilThe Burroughs ALGOL compiler was very fast ... impressed Dijkstra ... immediately wanted several machines for his Univ (Eindhoven) ... primary reason was that it was one-pass ... because of ALGOL declare-before-use ... and they had the fastest card readers in the industry.
B6500: Cactus stacks for concurrency. Tagged memory for security. A machine way ahead of its time.