JCM14h ago

Managed to go from

Info: DP16KD: 0/ 56 0% Info: MULT18X18D: 1/ 28 3% Info: TRELLIS_FF: 1612/ 24288 6% Info: TRELLIS_COMB: 5705/ 24288 23% Info: Max frequency for clock '$glbnet$main_clk': 25.20 MHz (PASS at 25.00 MHz)

to

Info: DP16KD: 1/ 56 1% Info: MULT18X18D: 1/ 28 3% Info: TRELLIS_FF: 515/ 24288 2% Info: TRELLIS_COMB: 2480/ 24288 10% Info: Max frequency for clock '$glbnet$main_clk': 57.34 MHz (PASS at 25.00 MHz)

by replacing my hacky register-based string templating solution with a (still hacky) RAM-based one and by setting ranges on all my integer.

Feels good~



RE: https://wafrn.jcm.re/fediverse/post/627f72e6-73a3-415e-b5a7-88dbeb959b1a
#vhdl #icepi-zero #fpga #hdl #hardware-development #this-is-gonna-be-so-incredibly-cursed-in-the-end-xD
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Hacker NewsApr 9

PicoZ80 – Drop-In Z80 Replacement

https://eaw.app/picoz80/

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picoZ80

picoZ80 - RP2350 based drop-in Z80 CPU replacement with WiFi management interface. Cycle-accurate Z80 emulation using PIO for Sharp MZ-700 and other vintage computers.

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