This chip is special,
(https://tinytapeout.com/chips/ttsky25b/)

- it has designs made by hobbyists
- and, more importantly, it has two #FemtoRV designs in it !!
- these two FemtoRV designs were authored by others

What is FemtoRV ? It is a super simple RiscV processor that we designed with @Mecrisp because we were boring during COVID...),
More information here:
https://github.com/BrunoLevy/learn-fpga/

I am super excited, can't wait to see whether these 200 lines of VERILOG can be turned into a real Risc-V CPU on a chip !

I am happy to announce the release of a longwave software defined radio which I designed at work for experiments with #DSP algorithms, running on the #ULX3S #FPGA board. The user interface is based on #Mecrisp #Forth running on the #FemtoRV, and the signal chain contains a pipelined FFT designed by Dan Gisselquist. Many thanks to Ulixxe for their USB-CDC implementation!

https://github.com/mb-sat/ulx3s-longwave-sdr
https://codeberg.org/Mecrisp/ulx3s-longwave-sdr

I am looking for a #riscv #FPGA soft core which uses large muliplexers to do ALU math in a single clock cycle. It is for the #gatemate FPGA. GateMate has large 8 input multiplexers which only need two layers to choose between 32 registers.

There are so many RISC-V soft cores it is hard to know which one to choose. On smaller FPGAs, some soft cores like the #FemtoRV store the registers in memory, so first they have to load 2 registers.

https://github.com/PythonLinks/awesome-gatemate

https://github.com/PythonLinks/awesome-risc-v-soft-cores