You can find the source code on GitHub (I'm considering moving to Codeberg): https://github.com/projf/isle

Includes everything you need for:
* @machdyne Lakritz (Lattice ECP5)
* Digilent Nexys Video (Xilinx XC7)
* Radiona #ULX3S (Lattice ECP5)
* Verilator simulator with SDL (Linux/macOS/Windows)

Board testing in advance of #FPGAFriday. The answer was 42. #ULX3S

And a quick lunchtime shot of ๐Ÿ๏ธ Isle.Computer running on #ULX3S.

Simulation may be practical for software dev, but it feels so much better seeing it running on real hardware. This is #riscv asm decoding UTF-8 sent over UART to Isle hardware running on #fpga. Verilog and asm written by hand. ๐Ÿ˜Š

Work on ๐Ÿ๏ธ Isle #FPGA computer input chapter continues. Here Iโ€™m testing UART with #ULX3S dev board.

You can find the open-source designs and instructions for ๐Ÿ๏ธ Isle FPGA computer at: https://github.com/projf/isle

You can run Isle on Linux/Mac/Windows under simulation, and it's really easy to set up.

Plus, there's board support #ULX3S, @machdyne Lakritz, and Digilent Nexys Video.

GitHub - projf/isle: Isle FPGA Computer

Isle FPGA Computer. Contribute to projf/isle development by creating an account on GitHub.

GitHub

Isle computer supports @machdyne Lakritz, Digilent Nexys Video, and Radiona #ULX3S.

And it's easy to run Isle's simulation; for example on macOS with brew installed:

brew install verilator sdl2
cd isle/boards/verilator/ch04
make
./obj_dir/ch04 # run sim

Isle.Computer hardware text mode on #ULX3S. With 2x scaling and horizontal offset to centre at 1366x768. Iโ€™m getting ready to release the next chapter and hardware designs. #FPGA

@WillFlux

Thanks a lot for the new post! Works perfectly on the #Radiona #ulx3s #fpga

If you have a @machdyne Lakritz, Digilent Nexys Video, or Radiona #ULX3S #FPGA board, please give the latest ๐Ÿ๏ธ Isle design a test and let me know how you get on. ๐Ÿ™

2D drawing blog post: https://projectf.io/isle/2d-drawing.html
FPGA board Support: https://github.com/projf/isle/tree/main/boards

Isle 2D Drawing

I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430
FemtoMSP430

MSP430 Playground for ULX3S

Codeberg.org