Tudor TimiJan 30, 2025
Yet again, I run into the problem that a crappy #semiEDA tool wrapper can't properly handle multi-token arguments (i.e. `wrapper --tool-arg 'some value'` leads to something like `tool --arg some value`). I'm getting pretty sick and tired of running into this again and again and again.
Daniel GrosseDec 16, 2024

🎉 Exciting News! Our paper "Using virtual prototypes and metamorphic testing to verify the hardware/software-stack of embedded graphics libraries" has been accepted for publication in Integration, the VLSI Journal.

📄 PDF (open access): https://www.sciencedirect.com/science/article/pii/S0167926024001846
📂 MT Approach GitHub: https://github.com/ics-jku/mt-graphlib-framework
📂 RISC-V VP++ GitHub: https://github.com/ics-jku/riscv-vp-plusplus

#VP #MetamorphicTesting #SemiEDA #SystemC
#VirtualPrototype #MetamorphicTesting #Embedded #GraphicLibrary #SystemC #RISCV #SemiEDA #journal

Murat EskiyerliJan 8, 2024
A new release candidate for Revolution EDA is uploaded to Github, including a new layout editor with hierarchical GDS export capability, layout parametric cells, SPICE subcircuit import, improved hierarchical netlisting, and a lot more:
https://github.com/eskiyerli/revedaRelease
#semiEDA
GitHub - eskiyerli/revedaRelease: This repository is for (pre-)release versions of the Revolution EDA.

This repository is for (pre-)release versions of the Revolution EDA. - GitHub - eskiyerli/revedaRelease: This repository is for (pre-)release versions of the Revolution EDA.

GitHub
RISC-VJul 25, 2023

RT from Daniel Payne (@Daniel_J_Payne)

RISC-V engineers can do logical ECOs faster using formal technology, see how at this Synopsys webinar with a speaker from SiFive. July 26th, 10-11AM PDT. https://marketingeda.com/event/a-novel-approach-to-implementing-logical-ecos-with-synopsys-formality-eco-on-high-performance-risc-v-cores/ #SemiEDA #SemiWiki

Original tweet: https://twitter.com/Daniel_J_Payne/status/1683590226432901120

A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores - Marketing EDA

RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU… Read More »A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores

Marketing EDA
RISC-VMar 14, 2023

RT from Daniel Payne (@Daniel_J_Payne)

TSMC, Synopsys, proteanTecs, RISC-V and Infineon will be at the GSA 2023 European Executive Forum, 14-15 June, Munich. https://marketingeda.com/event/gsa-2023-european-executive-forum/ #SemiEDA #SemiIP

Original tweet : https://twitter.com/Daniel_J_Payne/status/1635376968026972169

GSA 2023 European Executive Forum - Marketing EDA

Dealing with Uncertainty The global economy is sending mixed messages, and with every new data release comes a new batch of upbeat or defeatist headlines. Uncertainty remains if inflation is… Read More »GSA 2023 European Executive Forum

Marketing EDA
GrepFeb 4, 2023
Apple says using its own chips gives it a 'unique advantage' over PC industry #SemiEDA https://finance.yahoo.com/news/apple-says-using-its-own-chips-gives-it-a-unique-advantage-over-pc-industry-202103077.html
Yahooist Teil der Yahoo Markenfamilie

RISC-VDec 20, 2022

RT from Semiconductor Engineering (@SemiEngineering)

10 technical papers added this week https://semiengineering.com/chip-industrys-technical-paper-roundup-dec-20/
#RISCV #semiconductor #lowpower #HardwareSecurity #SRAM #graphene #chiplets
@UTAustin @ucsbcs @aalto @AuburnU @FLEETCentre @UMich @ethzurich @ETH_en
#5G #fuzzing #semiEDA

Original tweet : https://twitter.com/SemiEngineering/status/1605238496696094720

Chip Industry’s Technical Paper Roundup: Dec. 20

Heterogeneous ultra-low-power Linux capable RISC-V SoC; fuzzing HW; layout automation; parallelization of 5G PUSCH on RISC-V; repurposed Josephson Junctions; chirality logic gates; SRAM security risk; fast-lock digital clock generator for chiplets; suppressing vibrations on graphene devices; RL for design space exploration.

Semiconductor Engineering
RISC-VDec 19, 2022

RT from Semiconductor Engineering (@SemiEngineering)

Week In Review: Design, Low Power https://semiengineering.com/week-in-review-design-low-power-225/
#semiEDA #RISCV #verification #embedded #cybersecurity #GPNPU @quadric_io @Codasip #fusion #lowpower #semiconductor

Original tweet : https://twitter.com/SemiEngineering/status/1604701031308222464

Week In Review: Design, Low Power

Nuclear fusion's potential impact on IC design; RISC-V verification, embedded development, new cores; testing network cybersecurity; funding for GPNPU IP.

Semiconductor Engineering
GrepDec 14, 2022
Interesting article discussing the state of #semiconductor #SemiEDA
Is Moore’s law actually dead this time? Nvidia seems to think so https://arstechnica.com/?post_type=post&p=1883729
Is Moore’s law actually dead this time? Nvidia seems to think so

Chips "going... down in price is a story of the past," CEO says.

Ars Technica
RISC-VAug 4, 2022

RT from Daniel Payne (@Daniel_J_Payne)

The SemIsrael Tech Webinar for September 13th is being planned, at least Imperas is presenting on RISC-V processor verification. More speakers to be added. https://marketingeda.com/event/semisrael-tech-webinar-3/ #SemiEDA #SemiIP

Original tweet : https://twitter.com/Daniel_J_Payne/status/1555221510301749248

SemIsrael Tech Webinar - Marketing EDA

Stay Tuned… Advanced RISC-V processor verification and methodologies This talk will outline the latest advances in RISC-V functional verification to address the demands of high-reliability and automotive applications, including the innovations in processor designs with features such as: out-of-order pipelines, hardware multi-threading, multi-hart, custom extensions and advanced privileged modes, plus vector accelerators. Key updates will… Read More »SemIsrael Tech Webinar

Marketing EDA