For some of the most compelling keynotes and smaller company innovation showcased at the #RISCVSummit, read #SemiWiki’s recent Launchpad Showcase to “get a feeling for the magnitude of the RISC-V momentum.” https://semiwiki.com/events/339138-risc-v-summit-buzz-launchpad-showcase-highlights-smaller-company-innovation/?hss_channel=tw-2694452875 #RISCVeverywhere
Original tweet: https://twitter.com/risc_v/status/1740826269296542044
One of the goals of the recent RISC-V Summit was to demonstrate that the RISC-V movement is real – major programs by large organizations committing to development around the RISC-V ISA. I would say this goal was achieved. Many high-profile announcements and aggressive, new architectures based on RISC-V were presented. On day one, compelling keynotes…
“...RISC-V processors are finding a fit to address the huge processing demands of embedded AI.” #SemiWiki has more on how @axiomise accelerates RISC-V designs with next gen formalISA: https://riscv.org/news/2023/12/risc-v-summit-buzz-axiomise-accelerates-risc-v-designs-with-next-generation-formalisa/?hss_channel=tw-2694452875 #RISCVeverywhere
Original tweet: https://twitter.com/risc_v/status/1737231835891925244
RT from Daniel Payne (@Daniel_J_Payne)
RISC-V engineers can do logical ECOs faster using formal technology, see how at this Synopsys webinar with a speaker from SiFive. July 26th, 10-11AM PDT. https://marketingeda.com/event/a-novel-approach-to-implementing-logical-ecos-with-synopsys-formality-eco-on-high-performance-risc-v-cores/ #SemiEDA #SemiWiki
Original tweet: https://twitter.com/Daniel_J_Payne/status/1683590226432901120
RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU… Read More »A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
Holden Green
RISC-V