After a long hiatus, I finally wrote a new blog post: https://blog.verificationgentleman.com/2026/03/01/coverage-extensibility-in-systemverilog-2023 . This one's about the "embedded covergroup inheritance" feature added to SystemVerilog by IEEE 1800-2023. Is what I wrote in 2015 about coverage extensibility now obsolete? Read the post to find out!
Coverage Extensibility in SystemVerilog-2023
Quite a while back I wrote a series of posts about coverage extensibility in SystemVerilog. In the first post we looked at how to use policy classes to implement extensible coverage collectors, where ignore bins can be tweaked via class parameters. The second post explored a dynamic flavor of this approach, using constructor arguments instead. Finally, the third post tied everything together by looking at how these approaches interact with UVM and the factory.
