idea:
what if instead of rushing to implement hardware support in a particular GPPL for a pre-existing platform or device we wrote #SystemRDL specification for it first
it doesn't cost almost any extra efforts to write but offers some extra flexibility, e.g.
- the interface types and common access logic may be generated for any GPPL, including those added later on, without modifying the description itself
- the documentation generated from the RDL files may be in a sense even better than that provided by the h/w vendors (more homogeneous and adaptive at least, not just a bad-quality PDF)
- device emulation models, so you could test your drivers on multiple devices installed in the system (VM) while in reality you have none
- synthesisable register blocks may be generated as well, easing the development of compatible hardware

the vendors aren't going to be happy about all these perspectives though

for #SystemRDL and similar languages there are (synthesisable) register block generators, having #AXI or AXI Lite on one end and a bunch on signals corresponding to the fields on another
similar generated blocks for parsing and forming AXI Stream should be a thing as well, turning an octet stream into a structure together with a validity and no-longer-needed signals, or vice versa

#HDL #VHDL #SystemVerilog #Verilog #HLS