The irony: the entire RISC-V base ISA (RV64GC) is beautifully RISC: simple opcodes, fixed 32-bit instructions (+ compressed), load/store architecture, no flags, no implicit state. Then RVV comes along and throws all those principles out the window: global implicit state, microcode-like behavior, variable semantics of the same instruction.
Because vsetvli changes the semantics of all subsequent V-instructions based on the current VLEN configuration. For a JIT compiler in an Emulator and for an Emulator in general, this means having to continuously track the vtype state and react to any changes, a fundamental contradiction to the principle of statically analyzable instructions. It feels like the RISC-V Foundation sacrificed the simplicity and elegance of the RISC principle to create a powerful but extremely complex "super-SIMD" that is difficult to efficiently map in a JIT. A more traditional SIMD extension with fixed vector widths and clearly defined instruction semantics would have been much more JIT-friendly. The upcoming P extension does go in that direction, but it is primarily targeted at embedded and low-power applications rather than high-performance computing.
#riscv #riscv64 #emulation #pasriscv #object_pascal #delphi #free_pascal
Habr
Scientific Pascal
Benjamin Rosseaux 
