FLF
@icepi-zero-bot \o/
My python script finally works for sending hdl code with mastodon and toot ;)
I'll publish it soon.
Yann SionneauIt's hard to find time to post updates on all the progress I am making on the SucréLA #opensource #FPGA based Logic Analyzer 🥵
But it's going forward full steam! 🚂 🚄
Lots of fixes and robustification pushed. 🔧 ✅
It's now working pretty well in PulseView sampling as fast as 128 Msps which is pretty good for a first 2-boards-plugged-together-prototype. 😍
I'm even mostly using it to debug itself now! 🤳
So, to "conclude" yesterday's debug session, it seems that increasing the number of parallel libusb async bulk tranfers from 16 to 32 fixes the issue.
No more late USB reads from the host!
If someone has theories on how to "calibrate" this number of parallel transfers ... is there a formula somewhere?
I still don't understand yet why 32 was not enough and what makes those fail.
I found the issue! 🥳
Can you see it? :) 🔬 🐛
#opensource #fpga #ecp5 #oshw #SucreLA #logicielslibres #electronics #soc
I'm dogfooding SucréLA! 🐶
I'm currently using it to .... debug itself!
This is showing HSPI packets and the timing of the MCU IRQ handlers for HSPI and USB.
So cool to use it for real and to debug itself :)
#opensource #fpga #ecp5 #oshw #SucreLA #logicielslibres #electronics #soc
SucréLA open-source sw/hw/gateware Logic Analyzer now supports a new exciting feature: x2 and x4 oversampling ! 🥳
Meaning that while the capture pipeline in the SoC runs @ X MHz on N probes, it can now also sample:
* N/2 probes @ 2*X MHz 😍
or
* N/4 probes @ 4*X MHz 🥵
While continuously streaming data to the host PC running sigrok/PulseView via USB 3.0 ⚡
Wanna see how this feature has been developed? 🫣
https://gitlab.com/yannsionneau/SucreLA/-/commit/fbba0ced39b5d9e3c3f4cf9f92c592914d8afee2 🤓
#opensource #fpga #ecp5 #logicielslibres #oshw #soc #SucreLA
I'm making lots of progress on the HydraSucréLA bringup! 🎺
Open source sw/hw/gateware logic analyzer incoming!
It's already capturing 🎉 🥳
