The @RadionaOrg ULX3S hub site now honors device dark mode! Sunglasses no longer needed 😎

I also added a Tiny Tapeout section, as (pending a few Pull Request merges) @latticesemi #ECP5 FPGA support for testing your ASIC design on the #ULX3S is coming to @tinytapeout

@icepi-zero-bot @linuxfr.org.news
It's in french

https://linuxfr.org/users/martoni/journaux/de-la-synthese-et-du-test-fpga-grace-au-fediverse

#ecp5 #linuxfr #vhdl #hdmi

It's hard to find time to post updates on all the progress I am making on the SucréLA #opensource #FPGA based Logic Analyzer 🥵

But it's going forward full steam! 🚂 🚄

Lots of fixes and robustification pushed. 🔧 ✅

It's now working pretty well in PulseView sampling as fast as 128 Msps which is pretty good for a first 2-boards-plugged-together-prototype. 😍

I'm even mostly using it to debug itself now! 🤳

#ecp5 #soc #oshw #SucreLA #fpga

I'm dogfooding SucréLA! 🐶

I'm currently using it to .... debug itself!

This is showing HSPI packets and the timing of the MCU IRQ handlers for HSPI and USB.

So cool to use it for real and to debug itself :)

#opensource #fpga #ecp5 #oshw #SucreLA #logicielslibres #electronics #soc

SucréLA open-source sw/hw/gateware Logic Analyzer now supports a new exciting feature: x2 and x4 oversampling ! 🥳

Meaning that while the capture pipeline in the SoC runs @ X MHz on N probes, it can now also sample:
* N/2 probes @ 2*X MHz 😍
or
* N/4 probes @ 4*X MHz 🥵

While continuously streaming data to the host PC running sigrok/PulseView via USB 3.0 ⚡

Wanna see how this feature has been developed? 🫣

https://gitlab.com/yannsionneau/SucreLA/-/commit/fbba0ced39b5d9e3c3f4cf9f92c592914d8afee2 🤓

#opensource #fpga #ecp5 #logicielslibres #oshw #soc #SucreLA