Good news!
I'll be at #FOSDEM this year again.
You can meet me at @xcpng stand , see you in building H :)
I'll also be presenting the SucréLA open source logic analyzer: https://fosdem.org/2026/schedule/event/WSKHHU-sucrela_open_source_usb_3_0_logic_analyzer_based_on_fpga/
See you around!
And look at what I've just received ... 🎁
PCBs + stencil 😍 🍾
A few days after receiving the components from LCSC. 📦
It's still xmas! 🎄
The taste of layout and routing a high speed 6 layers PCB at night while sipping a de-stressing infusion :)
It's hard to find time to post updates on all the progress I am making on the SucréLA #opensource #FPGA based Logic Analyzer 🥵
But it's going forward full steam! 🚂 🚄
Lots of fixes and robustification pushed. 🔧 ✅
It's now working pretty well in PulseView sampling as fast as 128 Msps which is pretty good for a first 2-boards-plugged-together-prototype. 😍
I'm even mostly using it to debug itself now! 🤳
So, to "conclude" yesterday's debug session, it seems that increasing the number of parallel libusb async bulk tranfers from 16 to 32 fixes the issue.
No more late USB reads from the host!
If someone has theories on how to "calibrate" this number of parallel transfers ... is there a formula somewhere?
I still don't understand yet why 32 was not enough and what makes those fail.
I found the issue! 🥳
Can you see it? :) 🔬 🐛
#opensource #fpga #ecp5 #oshw #SucreLA #logicielslibres #electronics #soc
I'm dogfooding SucréLA! 🐶
I'm currently using it to .... debug itself!
This is showing HSPI packets and the timing of the MCU IRQ handlers for HSPI and USB.
So cool to use it for real and to debug itself :)
#opensource #fpga #ecp5 #oshw #SucreLA #logicielslibres #electronics #soc
Yann Sionneau