refining a diy hardware design
workflow and sharing.
There's not any clever insight I will add to
the classic designs I build. But I hope that
my modest presentation of these elegant
ideas will inspire others to break out of
the confines of our infinite scroll loops.
To experiment with simple concepts and
hopefully enrich their own understanding
of engineering concepts.
Each mechanical component of the variable #capacitor was modeled with #OpenSCAD.
Which I used to generate meshes for electrostatic modeling w/ #ElmerFEM.
scriptable w/🐍 openscad: csg -> freecad: stl -> ElmerGUI: mesh
I created an assembly in OpenSCAD but my progress was slow (NopSCADlib helped though).
Which OpenSCAD design patterns exist for sensible parameterization of component mating?
In the end, I relented and used FreeCAD V1.0's assembly workbench for mating components.
A quick study of start-up in the Hartley:
A current impulse is injected into the Hartley's LC tank.
The capacitive branch offers a lower impedance (1/jωC) to the impulse's leading edge (large ω) than the inductive branch (jωL).
While the injected current is constant, the inductive branch's current increases.
The impulse ends and the capacitive branch begins to discharge through the coils.
The two branches exchange stored energies and oscillations will commence.
When analyzing the Hartley (Fig1), it's easiest to first remove the biasing details.
Node numbering was adjusted from my last post. An s-domain analysis confirms
that the oscillation frequency is sqrt(1/(L1+L2)C). This technique follows Sedra/Smith.
The variable capacitor will tune roughly 10-100pF.
Fig2 is an electrostatic estimate (24pF) of 1 rotating & 2 stationary plates using ElmerFEM.
A 20uH ferrite toroid at 4MHz is feasible. It'll need some fixed capacitance...
I've got a new paper out on eprint: Monitoring tamper-sensing meshes using low-cost time-domain reflectometry.
In the paper, I wrote up how you can build a ~200 ps resolution time-domain reflectometer from an STM32 and some cheap display bus redriver ICs. The circuit is sensitive enough to distinguish several identical copies of the same test specimen PCB from manufacturing tolerances!
blog post: https://jaseg.de/blog/paper-sampling-mesh-monitor/
paper preprint: https://eprint.iacr.org/2025/1962
Continuing this paused project started a few years ago… Meanwhile the Raspberry team released the #RP2350 which is a significant upgrade to the #RP2040, offering more power for signal processing.
The PCB is populated with the SMD components and the lowest through-hole parts.
I started the mechanical work. I only have a hand-held drill and as usual I struggle to place the holes right. 😬
Before continuing soldering, I have to check if everything is fitting and vertically aligning well.
Put together the phase delay oscillator in the #deadbug #homebrew style. At 9V, the 1133 Hz sinusoidal output is distorted (similar to simulation). Dropping the input voltage by a factor of three yields a cleaner waveform. I left the lead (top right) at the output filter untrimmed, I'll use it to hook the board into it's makerel tin chassis.
#gnuplot plots of the phase-delay oscillator's outputs.
In order to get #oscillations going, the #transient analysis includes the `UIC` directive which asks #Xyce to forgo the typical operating point calculation, and instead use the supplied initial values (see `.ic` line). The specific initial values used should be non-zero, it is simplest to set the battery terminal node (n0) to some non-zero value.
The #Xyce #simulation of the PDO is here: https://codeberg.org/rjp/diy-tm/src/commit/0b9b12dd28ad2b7ed67f2dd0c2df811469916dae/pdo/sim/osc.sp#
Karl Matthias 🇺🇦
jaseg @ 39C3 (☎️ 57933)
Firesledge 🔥🛷