niko
Gareth HalfacreeThen something for the #Verilog and #Factorio crowd to bond over: a tool for taking a Verilog chip design and putting into the game... as a functional factory.
Demos of its capabilities go all the way up to a 32-bit #RISCV CPU...
Khronos GroupKeynote at IWOCL 2026: Paulius Velesko presents chipStar โ compiling unmodified CUDA/HIP code into OpenCL & SPIR-V fat binaries that run on Intel, AMD, NVIDIA, ARM, and RISC-V hardware. No recompilation needed.
Join us at IWOCL 2026, May 6โ8 in Heilbronn, Germany to hear more.
View the full program at: https://www.iwocl.org/iwocl-2026/conference-program/
#IWOCL2026 #OpenCL #SYCL #CUDA #HPC #HeterogeneousComputing #RISCV #CUDA
Ekaitz Zarraga ๐น
cnx-software.comAlibaba XuanTie C950 โ A powerful, RVA23-complaint 64-bit RISC-V core for Edge AI computing
Alibaba XuanTie C950 โ A powerful, RVA23-complaint 64-bit RISC-V core for Edge AI computing
Alibaba has introduced the XuanTie C950 high-performance, 64-bit multi-core CPU IP with an out-of-order superscalar microarchitecture, RVA23 profile compliant, and support for "all optional extensions" such as Vector Crypto, Zacas, and Zama16. The company also says the XuanTie C950 supports the proprietary XuanTie AME (Attached Matrix Extension) ISA and supports integration with the company's XuanTie TPE (Tensor Processing Engine) IP. The new 64-bit RISC-V core will be found in SoCs with up to eight cores per cluster, targeting high-performance applications, such as cloud computing, edge computing, and AI computing. XuanTie C950 specifications: Architecture - RVA23 Profile Up to 8x cores clocked at 3.2 GHz; 22+/GHz Specint2006 base, or a score of around 70 at 3.2 GHz Pipeline - Superscalar out-of-order microarchitecture with 8-wide decode Floating Point - RISC-V F/D Extension Vector - RISC-V Vector Extension v1.0 with Vector Crypto support Matrix - XuanTie TPE coprocessor integration (AME v0.5) Hypervisor -
Alibaba XuanTie C950 โ A powerful, RVA23-complaint 64-bit RISC-V core for Edge AI computing
Alibaba XuanTie C950 โ A powerful, RVA23-complaint 64-bit RISC-V core for Edge AI computing
Ludovic HenryHappy to share what I've been working on these past weeks at RISE: free #riscv GitHub Actions runners for any open source project.
Real hardware, not QEMU. Ephemeral #kubernetes pods on bare-metal RISC-V nodes.
1. Install the #github app:
- for orgs https://github.com/apps/rise-risc-v-runners
- for personal accounts: https://github.com/apps/rise-risc-v-runners-personal
2. Set `runs-on: ubuntu-24.04-riscv` in your workflow, and you're good to go.
Docs: https://riseproject-dev.github.io/riscv-runner/
Blog post: https://riseproject.dev/2026/03/24/announcing-the-rise-risc-v-runners-free-native-risc-v-ci-on-github/
#riscv #github #ci #cicd
Project InsanityAfter many years upstreaming patches, here's our small but extensive #RISCV #NixOS homeserver ๐คฉ https://project-insanity.org/2026/03/25/this-small-risc-v-homeserver-can-host-almost-anything/
This small RISC-V homeserver can host almost anything ๐
Getting NixOS running with various web services and features on this StarFive VisionFive 2 SBC took some years but finally it's taking shape. If you're reading this blog post, you reached our new tiny homeserver in the basement of our living community in Karlsruhe, Germany. It's running behind a standard cable internet NAT and a [...]
Banana Pi Open Source Hardware