I see various articles about #loongarch, #zhaoxin and even #riscv CPUs that usually end with "it doesn't outperform a first-gen Ryzen or Haswell".
Big deal. It doesn't have to. It's targeting a different market.
It's far more important to have a good enough sovereign supply chain for the billion low-end office desktops that make a bureaucracy and economy tick. If relations collapse, gamers will have to make do with less.
DongshanPI K510 SoM appears with dual RISC-V cores and AI acceleration
What Can You Run on a 1960s Univac? Anything You’re Willing To Wait For!
Wow, what a fantastic write-up! Multi arch #k0s clusters, including #RISCV! Awesome!
https://opvolger.github.io/posts/10inch-rack/2026-04-14-multi-arch-k8s-cluster/
pero tras este inocente led hay un RISCV RV32I segmentado, con interrupciones y registro de control implementados. Capaz de ejecutar un total de 49 instrucciones diferentes....
Lo que vemos es sólo la punta del Icebereg!!! #FPGA #RISCV #AlhambraII
¡Ya tengo terminado el #RISCV segmentado para el curso del HADES-V! Pasa todos los tests. Ahora es el momento de sintetizarlo para la #AlhambraII En esta simulación se ve el momento exacto en el que se envía el patrón 0xAA a los LEDs de simulación
Este es el repo "en sucio", sin instrucciones y sin documentar todavía
https://github.com/Obijuan/Learn-System-Verilog/tree/main/wiki/log/examples/29-writeback
Hak Foo 
LinuxGizmos.com
VoidZeroOne 
Hublai (charismatic megafauna)
Hackaday
Tom Wieczorek
Obijuan