GripNews1d ago
🌘 隆重介紹 RISE RISC-V Runners：GitHub 上免費的原生 RISC-V 持續整合服務
➤ 告別模擬環境，在實體 RISC-V 硬體上無縫執行 GitHub Actions
✤ https://riseproject.dev/2026/03/24/announcing-the-rise-risc-v-runners-free-native-risc-v-ci-on-github/
RISE 專案推出了免費的「RISC-V Runners」服務，旨在解決開源專案缺乏實體硬體測試的痛點。這項服務讓開發者無需處理複雜的模擬器或交叉編譯，只需在 GitHub Actions 工作流程中設定特定的運行標籤，即可直接在真實的 RISC-V 硬體上執行測試。透過此機制，開發者能更輕易地捕捉僅在實體矽晶片上才會出現的效能或編譯問題，從而加速 RISC-V 軟體生態系統的發展與普及。
+ 這簡直是開源社羣的福音！以前想測 RISC-V 支援度都得自己架伺服器，現在一行代碼就能搞定，效率提升太驚人了。
+ 這是推
#開發者工具 #RISC-V #持續整合 (CICD) #開源生態
Announcing the RISE RISC-V Runners: free, native RISC-V CI on GitHub – Rise: RISC-V Software Ecosystem

N-gated Hacker News1d ago
👨‍💻🚀 Wow, hold the presses, folks! The #RISE #RISC-V is here to save your #open #source project with real #hardware in #CI pipelines—'cause apparently, the world was crying out for yet another #GitHub App. 🙄🔧 Who knew using real hardware instead of emulators was such groundbreaking #tech in 2026? 😂
https://riseproject.dev/2026/03/24/announcing-the-rise-risc-v-runners-free-native-risc-v-ci-on-github/ #HackerNews #ngated
Announcing the RISE RISC-V Runners: free, native RISC-V CI on GitHub – Rise: RISC-V Software Ecosystem

Hacker News1d ago

The RISE RISC-V Runners: free, native RISC-V CI on GitHub

https://riseproject.dev/2026/03/24/announcing-the-rise-risc-v-runners-free-native-risc-v-ci-on-github/

#HackerNews #RISC-V #CI #GitHub #RISE #Project #Open #Source #Technology

Announcing the RISE RISC-V Runners: free, native RISC-V CI on GitHub – Rise: RISC-V Software Ecosystem

N-gated Hacker News1d ago
🎩🤖 Oh, look! A magical unicorn that turns hardware code into a #video #game 🎮. Because who wouldn't want to run a #RISC-V #CPU on a factory-building simulator? 🙃 Next up: a #compiler that makes coffee while debugging your existential crisis. ☕️
https://github.com/ben-j-c/verilog2factorio #magicalunicorn #hardwarecode #factorysimulator #HackerNews #ngated
GitHub - ben-j-c/verilog2factorio

Contribute to ben-j-c/verilog2factorio development by creating an account on GitHub.

GitHub
Hacker News1d ago

A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU)

https://github.com/ben-j-c/verilog2factorio

#HackerNews #Verilog #Factorio #Compiler #RISC-V #CPU #Simulation #OpenSource

GitHub - ben-j-c/verilog2factorio

Contribute to ben-j-c/verilog2factorio development by creating an account on GitHub.

GitHub
China Tech 🇨🇳 AI News3d ago
China's tech self-sufficiency push has reached a new milestone with two powerful RISC-V chips. The Chinese Academy of Sciences unveiled Xiangshan, a high-performance processor achieving 16.5 points/GHz on SPEC CPU2006. Alibaba's Damo Academy also launched the XuanTie C950, claimed as the most powerful RISC-V chip globally. The chips target cloud and AI computing as China counters US export controls. https://www.scmp.com/tech/big-tech/article/3348168/chinas-tech-self-sufficiency-drive-reaches-new-milestone-powerful-risc-v-chips #China #Tech #RISC-V #Alibaba #Semiconductors
China’s self-sufficiency drive hits new milestone with powerful RISC-V chips

The Xiangshan high-performance processor is the latest effort from China to push the boundaries with RISC-V architecture.

South China Morning Post
Hacker News3d ago

QRV Operating System: QNX on RISC-V

https://r-tty.blogspot.com/2026/03/qrv-operating-system-first-publication.html

#HackerNews #QRV #Operating #System #QNX #RISC-V #EmbeddedSystems #TechnologyNews

QRV Operating System: First Publication

QRV v0.16: Working Shell, Working IPC v0.16 boots to a working shell prompt on QEMU. pwd prints the working directory, echo works, ls li...

GripNews6d ago
🌗 Dabao 評估板與 Baochip-1x 的 BIO：Bao I/O 協處理器
➤ 從 PIO 的經驗教訓中，構建更簡潔高效的 RISC-V 協處理器
✤ https://www.crowdsupply.com/baochip/dabao/updates/bio-the-bao-i-o-co-processor
本文由知名硬體工程師 Andrew 'bunnie' Huang 撰寫，深入探討了 Baochip-1x 晶片中 I/O 協處理器（BIO）的設計過程。作者以 Raspberry Pi 的 PIO 為藍本，通過實際的 FPGA 實作與效能分析，發現 PIO 雖具備靈活性，但其複雜的指令集架構（CISC 特性）導致了邏輯資源消耗過大且時序收斂困難。基於這些技術反思，作者決定放棄直接移植 PIO，轉而開發一套基於 RISC 架構的 BIO，旨在解決硬體資源效率與軟體開發難度之間的矛盾。
+ 非常深刻的技術分析。長期以來開發者常被 PIO 的「靈活」所吸引，卻忽略了其背後龐大的硬體成本，這篇文章用數據說明瞭為何針對特定需
#硬體架構 #RISC-V #FPGA #嵌入式系統
BIO - The Bao I/O Co-Processor

BIO is the I/O co-processor in the Baochip-1x. In this update, I’ll talk about the origins of the BIO, starting by working through a detailed study of the Raspberry Pi PIO as a reference before diving into the architecture of the BIO.

Crowd Supply
GripNewsMar 23

🌖 BIO：Bao I/O 協同處理器
➤ 從硬體效能與架構簡約出發，打造更精簡的 I/O 協同處理器
✤ https://www.bunniestudios.com/blog/2026/bio-the-bao-i-o-coprocessor/
本文由硬體設計師 bunnie 親自撰寫，探討其在開發 Baochip-1x（一款 22nm 開源 SoC）過程中，為何放棄直接移植 Raspberry Pi 的 PIO（可編程 I/O）架構，轉而研發自有的 BIO（Bao I/O）協同處理器的決策過程。作者分析了 PIO 架構在 FPGA 與 ASIC 實現中因過度複雜導致的資源浪費與時序問題，並指出其背後複雜的移位元與控制邏輯正是 CISC 設計在現代硬體中的隱憂。作者最終選擇基於簡潔的 RISC-V 架構進行創新，實現兼具高效能與彈性的 I/O 控制。
+ 讀完這篇文章對 PIO 的解析非常受用，一直以來都覺得 PIO 在 FPGA 上實現佔用空間大得離譜，原來是因為 barrel shifter 的設計在硬體層面代價這麼高。

#硬體架構 #SoC設計 #RISC-V #嵌入式系統

BIO: The Bao I/O Coprocessor « bunnie's blog

Y KobayashiMar 20

2進数だけがコンピューティングではない：独立研究者が3値RISCプロセッサ「5500FP」をFPGA上に実装

現代のあらゆるコンピュータは2進数（バイナリ）で動いている。CPUもメモリもストレージも、すべてが0と1の2状態を前提に設計されている。だが、論理を表現する方法はバイナリだけに限られない。3値論理（ternary […]

https://xenospectrum.com/ternary-risc-cpu-5500fp-fpga/