China's tech self-sufficiency push has reached a new milestone with two powerful RISC-V chips. The Chinese Academy of Sciences unveiled Xiangshan, a high-performance processor achieving 16.5 points/GHz on SPEC CPU2006. Alibaba's Damo Academy also launched the XuanTie C950, claimed as the most powerful RISC-V chip globally. The chips target cloud and AI computing as China counters US export controls. https://www.scmp.com/tech/big-tech/article/3348168/chinas-tech-self-sufficiency-drive-reaches-new-milestone-powerful-risc-v-chips #China #Tech #RISC-V #Alibaba #Semiconductors
China’s self-sufficiency drive hits new milestone with powerful RISC-V chips

The Xiangshan high-performance processor is the latest effort from China to push the boundaries with RISC-V architecture.

South China Morning Post
QRV Operating System: First Publication

QRV v0.16: Working Shell, Working IPC v0.16 boots to a working shell prompt on QEMU. pwd prints the working directory, echo works, ls li...

🌗 Dabao 評估板與 Baochip-1x 的 BIO:Bao I/O 協處理器
➤ 從 PIO 的經驗教訓中,構建更簡潔高效的 RISC-V 協處理器
https://www.crowdsupply.com/baochip/dabao/updates/bio-the-bao-i-o-co-processor
本文由知名硬體工程師 Andrew 'bunnie' Huang 撰寫,深入探討了 Baochip-1x 晶片中 I/O 協處理器(BIO)的設計過程。作者以 Raspberry Pi 的 PIO 為藍本,通過實際的 FPGA 實作與效能分析,發現 PIO 雖具備靈活性,但其複雜的指令集架構(CISC 特性)導致了邏輯資源消耗過大且時序收斂困難。基於這些技術反思,作者決定放棄直接移植 PIO,轉而開發一套基於 RISC 架構的 BIO,旨在解決硬體資源效率與軟體開發難度之間的矛盾。
+ 非常深刻的技術分析。長期以來開發者常被 PIO 的「靈活」所吸引,卻忽略了其背後龐大的硬體成本,這篇文章用數據說明瞭為何針對特定需
#硬體架構 #RISC-V #FPGA #嵌入式系統
BIO - The Bao I/O Co-Processor

BIO is the I/O co-processor in the Baochip-1x. In this update, I’ll talk about the origins of the BIO, starting by working through a detailed study of the Raspberry Pi PIO as a reference before diving into the architecture of the BIO.

Crowd Supply

🌖 BIO:Bao I/O 協同處理器
➤ 從硬體效能與架構簡約出發,打造更精簡的 I/O 協同處理器
https://www.bunniestudios.com/blog/2026/bio-the-bao-i-o-coprocessor/
本文由硬體設計師 bunnie 親自撰寫,探討其在開發 Baochip-1x(一款 22nm 開源 SoC)過程中,為何放棄直接移植 Raspberry Pi 的 PIO(可編程 I/O)架構,轉而研發自有的 BIO(Bao I/O)協同處理器的決策過程。作者分析了 PIO 架構在 FPGA 與 ASIC 實現中因過度複雜導致的資源浪費與時序問題,並指出其背後複雜的移位元與控制邏輯正是 CISC 設計在現代硬體中的隱憂。作者最終選擇基於簡潔的 RISC-V 架構進行創新,實現兼具高效能與彈性的 I/O 控制。
+ 讀完這篇文章對 PIO 的解析非常受用,一直以來都覺得 PIO 在 FPGA 上實現佔用空間大得離譜,原來是因為 barrel shifter 的設計在硬體層面代價這麼高。

#硬體架構 #SoC設計 #RISC-V #嵌入式系統

BIO: The Bao I/O Coprocessor « bunnie's blog

2進数だけがコンピューティングではない:独立研究者が3値RISCプロセッサ「5500FP」をFPGA上に実装

現代のあらゆるコンピュータは2進数(バイナリ)で動いている。CPUもメモリもストレージも、すべてが0と1の2状態を前提に設計されている。だが、論理を表現する方法はバイナリだけに限られない。3値論理(ternary […]

https://xenospectrum.com/ternary-risc-cpu-5500fp-fpga/

Revoltă în UE? Zece state europene, inclusiv România, cer revizuirea planului de energie verde al Ursulei von der Leyen Acestia califica cadrul actual al legislației drept un „risc existențial” pentru numeroase sectoare industriale cheie 👉 https://c.aparatorul.md/wapua 👈 #certificatelorETS #critic #Deciziile #energie #Europa #europene #Evoluțiilegeopolitice #existențial #frână #Industrie #PactulVerde #planului #Proiectuleuropean #prosperității #Revoltă #Risc #Rom...
https://c.aparatorul.md/wapua
New to me #RISC toys! Not #RISCV, I think this is RISC 2? I know has a pair of R12000 processors in it if that helps...
🌖 Dabao 開發板與 Baochip-1x:設計理念、時機與背景揭祕
➤ 挑戰 ARM 壟斷,以 RISC-V 與 MMU 為嵌入式系統帶來「桌機級」安全
https://www.crowdsupply.com/baochip/dabao/updates/what-it-is-why-im-doing-it-now-and-how-it-came-about
Andrew 'bunnie' Huang 在文中深入探討了其開發 Baochip-1x 晶片的初衷與技術願景。他強調,該晶片的核心亮點在於整合了記憶體管理單元(MMU),打破了傳統小型嵌入式系統因 ARM M 系列架構限制而缺乏虛擬記憶體的現狀。儘管目前晶片的部分 RTL 仍非完全開源,但 bunnie 認為,在完全開放的矽晶片生態系統成熟前,採取「部分開源」策略是推動開源硬體普及、降低對封閉架構(如 ARM)依賴的務實作法。他期盼透過此舉,讓開發者能提前建立基於開源標準的軟體應用,從而實現長期的硬體自主。
+ 終於有嵌入式晶片願意在 MMU 下功夫了!一直以來被
#開發硬體 #RISC-V #開源硬體 #系統架構
What It Is, Why I'm Doing It Now, and How It Came About

As a subscriber to the “Dabao” campaign, you’re already aware of the Baochip-1x. This update fills in the backstory of what it is, why I’m doing it now, and how it came about.

Crowd Supply
🌖 RISC-V 架構運行速度緩慢的現實挑戰
➤ 軟體移植之路:為何 RISC-V 距離成為主流架構還有一段距離?
https://marcin.juszkiewicz.com.pl/2026/03/10/risc-v-is-sloooow/
本文由資深開發者 Marcin Juszkiewicz 分享他在 Fedora Linux RISC-V 移植工作中的觀察。他詳細說明瞭為 RISC-V 平臺進行軟體打包的繁瑣過程,並透過客觀數據指出,受限於當前硬體效能(處理器核心與記憶體限制),RISC-V 的軟體編譯時間遠高於 x86 或 ARM 架構,甚至不得不關閉 LTO(連結時間優化)以縮短時程。作者強調,若要使 RISC-V 成為 Fedora 的官方架構,必須提升硬體效能至企業級伺服器標準,並建議現階段透過 QEMU 模擬器進行大規模多核心編譯來緩解開發壓力。
+ 這數據太真實了,RISC-V 要進入伺服器領域,硬體算力確實是最大的瓶頸,光靠情懷很難普及。
+ 作者提到的 QEMU 模擬編譯策略很實用,在硬
#RISC-V #Fedora Linux #編譯效能 #軟體開發
RISC-V is sloooow – Marcin Juszkiewicz

143 vs 36 minutes is far too big difference

👨‍💻 Oh, look! Another gripping tale of an #ARM #developer lamenting the glacial pace of #RISC-V 🐌 while pretending to be productive with Fedora's bug circus. 🎪 But hey, at least he got 86 pull requests in—a testament to truly pioneering 🚀 the art of waiting around! 😂
https://marcin.juszkiewicz.com.pl/2026/03/10/risc-v-is-sloooow/ #Fedora #pullrequests #productivity #HackerNews #ngated
RISC-V is sloooow – Marcin Juszkiewicz

143 vs 36 minutes is far too big difference