At FCCM 2026 I saw a keynote by Onur Mutlu on abusing DRAM chip timings to have them perform vector (row) copies and even or/and/nand computations on entire rows, 'for free' (happens physically through capacitors charge). And this is on current, off-the-shelves DDR3/DDR4 memory!
Well, I've got a bunch of great FPGA boards featuring good old SDRAM chips and ...
It turns out RowClone is possible on older SDRAM chips!








