Flux
Happy #FPGAFriday. I'm starting work on the next part of 🏝️Isle #FPGA Computer. I'm looking at input and the early system library. UTF-8 is surprisingly easy to decode in assembler; that's not some sort of humble brag, it's a testament to the design of UTF-8.
Happy #FPGAFriday. The hardware for the next installment of 🏝️ Isle #FPGA Computer is ready; now I'm working on docs, a new blog post, and an update for my sponsors. I'm aiming for a public update next Friday.
It can be difficult to let your imperfect creations feel the light of public scrutiny, but a project like this only thrives with the thoughts and contributions of many different people. 🙏
No FPGA for me today 😢, so I'd appreciate hearing about your hardware projects. #FPGAFriday
Hello hardware friends, it's a hot #FPGAFriday on the south coast. I'm writing tests and docs today, which is surprisingly satisfying if it's for a project you care about.
What are you working on today?
It's about time I updated my recommended #FPGA links. Send me a suggestion this #FPGAFriday. 😊 https://projectf.io/recommended-fpga-sites/
Recommended FPGA Sites
My favourite FPGA resources from across the Internet. Last updated May 2025. FPGA Learning Resources Black Mesa Labs FPGA Tutorial Bruno Levy’s Learn FPGA fpga4fun.com fpgacpu.ca Nandland Project F Tutorials :-) Sutherland HDL Verilog Pro Discussion 1BitSquared Discord (iCEBreaker) Digilent Forums (Arty and Nexys) Project F Discussions Radiona Discord (ULX3S) YosysHQ Community Slack Interesting Sites These sites are not 100% related to FPGAs but should interest hardware designers. Adiuvo Engineering Blog (Adam Taylor) benjamin.
Fearlessly generate your own clocks with Lattice ECP5 #FPGAs and Yosys. Includes worked examples for #ULX3S and easy to adapt to any dev board. Happy #FPGAFriday! @yosyshq https://projectf.io/posts/ecp5-fpga-clock/
ECP5 FPGA Clock Generation
Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL (phase-locked loop), you’re stuck running at the speed of your dev board oscillator. This post outlines the architecture of ECP5 PLL and provides several practical examples to get you started with generating custom clock frequencies. Generating your own clock frequencies is much more straightforward than it first appears.
It's the little differences... that drive you mad when supporting multiple #FPGA dev boards. 😢
Supporting #SPI flash on Arty S7 requires the STARTUPE2 primitive, while the A7 lets you access it via pin L16. #FPGAFriday
It's #FPGAFriday! Here's another peek at my current #FPGA project. This video shows Isle textmode, which supports coloured text (and backgrounds) and automatic scrolling. This capture is from Verilator/SDL, but it also runs on ECP5 and Xilinx 7 series FPGAs.