Inside the 8085 Microprocessor – Understanding Its Block Diagram

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8085 Microprocessor

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RISC-V Vector Extension overview
🔗 http://0x80.pl/notesen/2024-11-09-riscv-vector-extension.html

"The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.
[…]
The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations."

#RISCV #RISC_V #RVV #ComputerArchitecture #ISA #InstructionSetArchitecture #CPU #CPUs #processor #processors

RISC-V State of the Union — current highlights and roadmap of RISC-V by RISC-V's chief architect
🎞 https://yewtu.be/watch?v=_oLVPFQvJbI
Slides: https://riscv-europe.org/summit/2024/media/proceedings/plenary/Tue-11-30-Krste-Asanovic.pdf

#RISCV #RISC #CPU #CPUs #architecture #ComputerArchitecture #processor #processors #ISA #InstructionSetArchitecture #hardware

If it's $1 Trillion or if it's $7 Trillion, would it go towards Open #RISC #RISCV #OpenISA #ISA #InstructionSetArchitecture #OpenInstructionSetArchitecture ?

https://www.tomshardware.com/tech-industry/artificial-intelligence/jim-keller-responds-to-sam-altmans-plan-to-raise-dollar7-billion-to-make-ai-chips

On #RISCV in particular and the evolution of the #RISC approach to #CPU-design in general:

"Why The ISA Battles Aren't Over Yet" [2019], Hackaday (https://hackaday.com/2019/11/12/risc-v-why-the-isa-battles-arent-over-yet/).

#Hardware #Architecture #OpenRISC #POWER #SPARC #ISA #InstructionSetArchitecture

Software Defined… CPU?

Everything is better when you can program it, right? We have software-defined radios, software-defined networks, and software-defined storage. Now a company called Ascenium wants to create a software-defined CPU. They've raised millions of dollars to bring the product to market.

The materials are a bit hazy, but it sounds as though the idea is to have CPU resources available and let the compiler manage and schedule those resources without using a full instruction set. A system called Aptos lets the compiler orchestrate those resources.

If you are astute, you'll see this has some similarity to RISC and even more to VLIW computer architectures. For more detail, there's an interview with the company's CEO over on TheNextPlatform which has some insight into how the CPU will work.

In addition to RISC and VLIW, transport-triggered architecture shares in this philosophy, too, although there have only been a few commercial versions. So the idea of pushing work to the compiler isn't new. Time will tell if Ascenium's approach is really different and beneficial or, at least, if they can make more of a mark against the three or four big CPU makers.

Of course, if you really want to reconfigure your CPU, you could do it with an FPGA. Transport-triggered architectures have an advantage there because all you have is a single instruction along with addressable units. You can even microcode those for more complex instructions or emulations.

#computerhacks #news #cpu #instructionset #instructionsetarchitecture #isa #x86